Datasheet > IBM0164165PT3C-60

IBM0164165PT3C-60

更新时间： 2022-12-01 21:07:34

品牌	Logo	应用领域
国际商业机器公司 - IBM		动态存储器光电二极管
页数	文件大小	规格书
28页	480K
描述
EDO DRAM, 4MX16, 60ns, CMOS, PDSO50, 0.400 X 0.825 INCH, PLASTIC, TSOP2-50

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IBM0164165PT3C-60 数据手册

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Discontinued (8/98 - last order; 12/98 last ship)

IBM0164165B4M

x 1613/9, 3.3V, EDO. IBM0164165P4M x 1613/9, 3.3V, LP, SR, EDO.

IBM0164165B

IBM0164165P

4M x 16 13/9 EDO DRAM

Features

• 4,194,304 word by 16 bit organization

• Single 3.3 ± 0.3V power supply

• Dual CAS Byte Read/Write

• Performance:

-50

-60

• Extended Data Out (Hyper Page Mode)

t_RACRAS Access Time

t_CACCAS Access Time

50ns 60ns

13ns 15ns

25ns 30ns

84ns 104ns

• CAS before RAS Refresh

- 4096 cycles/Retention Time

t_AA

t_RC

Column Address Access Time

Cycle Time

• RAS only Refresh

- 8192 cycles/Retention Time

t_HPCEDO (Hyper Page) Mode Cycle Time 20ns 25ns

• 64ms Standard Power (SP) Retention Time

• 128ms Low Power (LP) Retention Time

• Hidden Refresh

• Max. Power Dissipation (-50)

- Active: 360mW

- Standby (SP version): 2.0 mA

- Standby (LP version): 0.2 mA

• Self Refresh (400 µA) - LP Version Only

• Read-Modify-Write

• Package: TSOP-50 (400mil x 825mil)

Description

The IBM0164165B/P is a dynamic RAM organized

4,194,304 words by 16 bits. This device is fabricated

in IBM’s most advanced CMOS silicon gate process

technology. The circuit and process design allow

this DRAM to achieve high performance and low

power dissipation. The IBM0164165B/P operates

with a single 3.3 ± 0.3V power supply, and inter-

faces directly with eitherTTL orCMOS levels. The 22

addresses required to access any bit of data are

multiplexed (13 are strobed with RAS, 9 are strobed

with CAS). They are packaged in a 50 pin plastic

TSOP type II (400mil×825mil). TheIBM0164165P

parts are low power devices supporting Self Refresh

and a 128ms retention time.

Pin Description

Pin Assignments (Top View)

RAS

LCAS / UCAS

Row Address Strobe

Column Address Strobe

Read/write Input

Address Inputs

Output Enable

Vcc

I/O0

I/O1

I/O2

I/O3

Vcc

I/O4

I/O5

I/O6

I/O7

Vcc

RAS

Vcc

Vss

I/O15

I/O14

I/O13

I/O12

Vss

I/O11

I/O10

I/O9

I/O8

A0 - A12

I/O0 - I/O15

V_CC

Data Input/output

Power (+3.3V)

Vss

V_SS

Ground

LCAS

UCAS

A12

A11

A10

Vss

Use is further subject to the provisions at the end of this document.

88H2012

GA14-4251-02

Revised 11/97

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