HY628400LLT2-55 PDF预览

HY628400LLT2-55

更新时间: 2025-09-06 23:57:15
品牌 Logo 应用领域
其他 - ETC 内存集成电路静态存储器光电二极管
页数 文件大小 规格书
9页 130K
描述
x8 SRAM

HY628400LLT2-55 数据手册

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HY628400 Series  
512Kx8bit CMOS SRAM  
DESCRIPTION  
FEATURES  
The HY628400 is a high-speed, low power and  
4M bits CMOS SRAM organized as 524,288  
words by 8 bits. The HY628400 uses Hyundai's  
high performance twin tub CMOS process  
technology and was designed for high-speed and  
low power circuit technology. It is particulary well  
suited for use in high-density and low power  
system applications. This device has a data  
retention mode that guarantees data to remain  
valid at the minimum power supply voltage of  
2.0V.  
·
·
·
·
Fully static operation and Tri-state outputs  
TTL compatible inputs and outputs  
Low power consumption  
Battery backup(L/LL-part)  
- 2.0V(min) data retention  
Standard pin configuration  
- 32pin 525mil SOP  
·
- 32pin 400mil TSOP-II  
(Standard and Reversed)  
Product  
No.  
HY628400  
Voltage  
(V)  
Speed  
(ns)  
55/70/85  
Operation  
Current(mA)  
10  
Standby Current(uA)  
Temperature  
(°C)  
0~70(Normal)  
L
LL  
30  
5.0  
100  
Note 1. Normal : Normal Temperature  
2. Current value are max.  
PIN CONNECTION  
A18  
A16  
A14  
A12  
A7  
Vcc  
32  
A18  
A16  
A14  
A12  
A7  
Vcc  
A15  
A17  
/WE  
A13  
A8  
Vcc  
A15  
A17  
/WE  
A13  
A8  
A18  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
1
2
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
1
2
1
2
A15  
31  
A16  
A14  
A12  
A7  
A17  
30  
3
3
3
/WE  
29  
4
4
4
A13  
28  
5
5
5
A8  
27  
A6  
A6  
A6  
6
6
6
A5  
A9  
A5  
A9  
26  
A9  
A5  
7
7
7
A11  
/OE  
A10  
/CS  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
A4  
A11  
25  
A11  
/OE  
A10  
/CS  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
A4  
A4  
8
8
8
A3  
/OE  
24  
A3  
A3  
9
9
9
A10  
23  
A2  
A2  
A2  
10  
11  
12  
13  
14  
15  
16  
10  
11  
12  
13  
14  
15  
16  
10  
11  
12  
13  
14  
15  
16  
/CS  
22  
A1  
A1  
A1  
A0  
A0  
I/O8  
21  
A0  
I/O1  
I/O2  
I/O3  
Vss  
I/O7  
20  
I/O1  
I/O2  
I/O3  
Vss  
I/O1  
I/O2  
I/O3  
Vss  
I/O6  
19  
I/O5  
18  
I/O4  
17  
SOP  
TSOP-II(Standard)  
TSOP-II(Reversed)  
PIN DESCRIPTION  
BLOCK DIAGRAM  
ROW DECODER  
I/O1  
A0  
Pin Name  
Pin Function  
/CS  
Chip Select  
Write Enable  
/WE  
MEMORY ARRAY  
1024x4096  
/OE  
Output Enable  
Address Input  
Data Input/Output  
Power(5.0V)  
Ground  
A0 ~ A18  
I/O1 ~ I/O8  
Vcc  
A18  
I/O8  
/CS  
/OE  
/WE  
Vss  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev.04 /Jan.99  
Hyundai Semiconductor  

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