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HY5V62DFP-7 PDF预览

HY5V62DFP-7

更新时间: 2024-01-15 09:12:09
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器内存集成电路
页数 文件大小 规格书
13页 374K
描述
Synchronous DRAM, 2MX32, 5.5ns, CMOS, PBGA90, 8 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, FBGA-90

HY5V62DFP-7 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA,
针数:90Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.29访问模式:FOUR BANK PAGE BURST
最长访问时间:5.5 ns其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-PBGA-B90JESD-609代码:e1
长度:13 mm内存密度:67108864 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:32
功能数量:1端口数量:1
端子数量:90字数:2097152 words
字数代码:2000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2MX32封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.2 mm
自我刷新:YES最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:8 mmBase Number Matches:1

HY5V62DFP-7 数据手册

 浏览型号HY5V62DFP-7的Datasheet PDF文件第1页浏览型号HY5V62DFP-7的Datasheet PDF文件第2页浏览型号HY5V62DFP-7的Datasheet PDF文件第3页浏览型号HY5V62DFP-7的Datasheet PDF文件第5页浏览型号HY5V62DFP-7的Datasheet PDF文件第6页浏览型号HY5V62DFP-7的Datasheet PDF文件第7页 
111Preliminary  
Synchronous DRAM Memory 64Mbit (2Mx32bit)  
HY5V62D(L/S)F(P) Series  
BALL DESCRIPTIONS  
SYMBOL  
TYPE  
DESCRIPTION  
Clock: The system clock input. All other inputs are registered to the SDRAM on the rising  
edge of CLK  
CLK  
INPUT  
Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will be one  
of the states among (deep) power down, suspend or self refresh  
CKE  
CS  
INPUT  
INPUT Chip Select: Enables or disables all inputs except CLK, CKE and DQM  
Bank Address: Selects bank to be activated during RAS activity  
INPUT  
BA0, BA1  
Selects bank to be read/written during CAS activity  
Row Address: RA0 ~ RA10, Column Address: CA0 ~ CA7  
Auto-precharge flag: A10  
A0 ~ A10  
INPUT  
Command Inputs: RAS, CAS and WE define the operation  
Refer function truth table for details  
RAS, CAS, WE INPUT  
DQM0 ~  
I/O  
Data Mask: Controls output buffers in read mode and masks input data in write mode  
Data Input / Output: Multiplexed data input / output pin  
DQM3  
DQ0 ~ DQ31  
VDD / VSS  
I/O  
SUPPLY Power supply  
VDDQ / VSSQ SUPPLY I/O Power supply  
NC  
-
No connection : These pads should be left unconnected  
Rev. 0.3 / Feb. 2005  
4

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