Datasheet > HY5V26FLFP-6I

HY5V26FLFP-6I

更新时间： 2023-01-15 00:00:00

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
12页	157K
描述
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, LEAD FREE, FBGA-54

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HY5V26FLFP-6I 数据手册

Synchronous DRAM Memory 128Mbit (8Mx16bit)

HY5V26F(L)F(P)-x(I) Series

DESCRIPTION

The Hynix HY5V26F(L)F(P)-x(I) series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory

applications which require wide data I/O and high bandwidth. HY5V26F(L)F(P)-xx(I) series is organized as 4banks of

2,097,152 x 16.

HY5V26E(L)F(P)-x(I) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and

outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve

very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-

quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or

can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-

stricted by a '2N' rule)

FEATURES

•

Voltage: VDD and VDDQ 3.3V supply voltage

All device pins are compatible with LVTTL interface

54 Ball FBGA (Lead or Lead Free Package)

•

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

All inputs and outputs referenced to positive edge of

system clock

•

Programmable CAS Latency; 2, 3 Clocks

Burst Read Single Write operation

•

Data mask function by UDQM, LDQM

Internal four banks operation

Auto refresh and self refresh

4096 Refresh cycles / 64ms

Operation temperature

HY5V26F(L)F(P)-XX Series: 0 ~ 70^oC

HY5V26F(L)F(P)-X(I) Series: -40 ~ 85^oC

ORDERING INFORMATION

Operation

Temp.

Part No.

Clock Frequency Organization

Interface

Package

HY5V26F(L)F(P)-5(I)

HY5V26F(L)F(P)-6(I)

HY5V26F(L)F(P)-7(I)

HY5V26F(L)F(P)-H(I)

200MHz

4Banks x

2Mbits x16

0 ~ 70^oC⁵⁾

40 ~ 85^oC⁶⁾

166MHz

143MHz

133MHz

LVTTL

54 Ball FBGA

Note: 1. HY5V26FF-x(I) Series: Normal power, Leaded.

2. HY5V26FLF-x(I) Series: Low power, Leaded

3. HY5V26FFP-x(I) Series: Normal power, Lead Free.

4. HY5V26FLFP-x(I) Series: Low power, Lead Free.

5. Commercial (0 ~ 70^oC)

6. Industrial (-40 ~ 85^oC)

Rev. 1.0 / June. 2007

123 4 5 6 7...12

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