Datasheet > HY5V28CF-K

HY5V28CF-K

更新时间： 2024-02-03 08:26:38

品牌	Logo	应用领域
其他 - ETC		内存集成电路动态存储器时钟
页数	文件大小	规格书
14页	117K
描述
x8 SDRAM

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

HY5V28CF-K 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	TFBGA, BGA54,9X9,32
针数：	54	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.02
风险等级：	5.92	访问模式：	FOUR BANK PAGE BURST
最长访问时间：	6 ns	其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	100 MHz	I/O 类型：	COMMON
交错的突发长度：	1,2,4,8	JESD-30 代码：	R-PBGA-B54
长度：	10.5 mm	内存密度：	134217728 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	8
功能数量：	1	端口数量：	1
端子数量：	54	字数：	16777216 words
字数代码：	16000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	16MX8	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装等效代码：	BGA54,9X9,32	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
刷新周期：	4096	座面最大高度：	1.07 mm
自我刷新：	YES	连续突发长度：	1,2,4,8,FP
最大待机电流：	0.001 A	子类别：	DRAMs
最大压摆率：	0.2 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	8.3 mm
Base Number Matches：	1

HY5V28CF-K 数据手册

HY5V28(L)F

4Banks x 4M x 8bits Synchronous DRAM

DESCRIPTION

The Hynix HY5V28C(L)F is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applica-

tions which require large memory density and high bandwidth. HY5V28C(L)F is organized as 4banks of 4,194,304x8.

HY5V28C(L)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs

are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high

bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device Balls are compatible with LVTTL interface

54Ball FBGA With 0.8mm of ball pitch

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full Page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by DQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY5V28CF-6

HY5V28CF-K

HY5V28CF-H

HY5V28CF-8

HY5V28CF-P

HY5V28CF-S

HY5V28CLF-6

HY5V28CLF-K

HY5V28CLF-H

HY5V28CLF-8

HY5V28CLF-P

HY5V28CLF-S

166MHz

133MHz

125MHz

100MHz

166MHz

133MHz

125MHz

100MHz

Normal

4Banks x 4Mbits

x 8

LVTTL

54Ball FBGA

Low power

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 0.1/Sep. 01

12 3 4 5 6 7...14

下载PDF

与HY5V28CF-K相关器件

型号	品牌	描述	获取价格	数据表
HY5V28CF-P	ETC	x8 SDRAM	获取价格
HY5V28CF-S	ETC	x8 SDRAM	获取价格
HY5V28CLF-6	ETC	x8 SDRAM	获取价格
HY5V28CLF-8	ETC	x8 SDRAM	获取价格
HY5V28CLF-H	ETC	x8 SDRAM	获取价格
HY5V28CLF-K	ETC	x8 SDRAM	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

HY5V28CF-K

HY5V28CF-K 技术参数

HY5V28CF-K 数据手册

与HY5V28CF-K相关器件

与HY5V28CF-K相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HY5V28CF-K

HY5V28CF-K 技术参数

HY5V28CF-K 数据手册

与HY5V28CF-K相关器件

与HY5V28CF-K相关文章

您还可以找

您在本页遇到什么问题？