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HY5V26EFP-6I PDF预览

HY5V26EFP-6I

更新时间: 2024-02-28 09:56:19
品牌 Logo 应用领域
海力士 - HYNIX 时钟动态存储器内存集成电路
页数 文件大小 规格书
12页 511K
描述
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, LEAD FREE, FBGA-54

HY5V26EFP-6I 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA54,9X9,32
针数:54Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.33访问模式:FOUR BANK PAGE BURST
最长访问时间:5.4 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):166 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:S-PBGA-B54
JESD-609代码:e1长度:8 mm
内存密度:134217728 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:54
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA54,9X9,32
封装形状:SQUARE封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.002 A
子类别:DRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:20宽度:8 mm
Base Number Matches:1

HY5V26EFP-6I 数据手册

 浏览型号HY5V26EFP-6I的Datasheet PDF文件第1页浏览型号HY5V26EFP-6I的Datasheet PDF文件第3页浏览型号HY5V26EFP-6I的Datasheet PDF文件第4页浏览型号HY5V26EFP-6I的Datasheet PDF文件第5页浏览型号HY5V26EFP-6I的Datasheet PDF文件第6页浏览型号HY5V26EFP-6I的Datasheet PDF文件第7页 
Synchronous DRAM Memory 128Mbit (8Mx16bit)  
HY5V26E(L)F(P)-xxI Series  
DESCRIPTION  
The Hynix HY5V26E(L)F(P)-xxI series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory  
applications which require wide data I/O and high bandwidth. HY5V26E(L)F(P)-xxI series is organized as 4banks of  
2,097,152 x 16.  
HY5V26E(L)F(P)-xxI is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and  
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve  
very high bandwidth. All input and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write  
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-  
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or  
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-  
stricted by a '2N' rule)  
FEATURES  
Voltage: VDD and VDDQ 3.3V supply voltage  
All device pins are compatible with LVTTL interface  
54 Ball FBGA (Lead or Lead Free Package)  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 or full page for Sequential Burst  
- 1, 2, 4 or 8 for Interleave Burst  
All inputs and outputs referenced to positive edge of  
system clock  
Programmable CAS Latency; 2, 3 Clocks  
Burst Read Single Write operation  
Data mask function by UDQM, LDQM  
Internal four banks operation  
Auto refresh and self refresh  
4096 Refresh cycles / 64ms  
Operation temperature : -40 ~ 85oC  
ORDERING INFORMATION  
Operation  
Temp.  
Part No.  
Clock Frequency Organization  
Interface  
Package  
HY5V26E(L)F(P)-5I  
HY5V26E(L)F(P)-6I  
HY5V26E(L)F(P)-7I  
HY5V26E(L)F(P)-HI  
200MHz  
166MHz  
4Banks x  
2Mbits x16  
-40 ~ 85oC  
LVTTL  
54 Ball FBGA  
143MHz  
133MHz  
Note: 1. HY5V26EF-xxI Series: Normal power, Leaded.  
2. HY5V26ELF-xxI Series: Low power, Leaded.  
3. HY5V26EFP-xxI Series: Normal power, Lead Free.  
4. HY5V26ELFP-xxI Series: Low power, Lead Free.  
5. HY5V26ESF(P)-xxI Series: Super Low power; Contact Hynix Office for product availability.  
Rev. 1.1 / Apr. 2005  
2

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