Datasheet > HY5DS283222BF-5

HY5DS283222BF-5

更新时间： 2024-02-01 12:45:04

品牌	Logo	应用领域
海力士 - HYNIX		时钟动态存储器双倍数据速率内存集成电路
页数	文件大小	规格书
28页	251K
描述
DDR DRAM, 4MX32, 0.6ns, CMOS, PBGA144, 12 X 12 MM, FBGA-144

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技术参数
数据手册

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HY5DS283222BF-5 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LFBGA, BGA144,12X12,32
针数：	144	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.02
风险等级：	5.92	访问模式：	FOUR BANK PAGE BURST
最长访问时间：	0.6 ns	其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	COMMON
交错的突发长度：	2,4,8	JESD-30 代码：	S-PBGA-B144
JESD-609代码：	e0	长度：	12 mm
内存密度：	134217728 bit	内存集成电路类型：	DDR DRAM
内存宽度：	32	功能数量：	1
端口数量：	1	端子数量：	144
字数：	4194304 words	字数代码：	4000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	4MX32
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFBGA	封装等效代码：	BGA144,12X12,32
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	1.8 V
认证状态：	Not Qualified	刷新周期：	4096
座面最大高度：	1.21 mm	自我刷新：	YES
连续突发长度：	2,4,8	最大待机电流：	0.025 A
子类别：	DRAMs	最大压摆率：	0.3 mA
最大供电电压 (Vsup)：	2.1 V	最小供电电压 (Vsup)：	1.75 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	12 mm
Base Number Matches：	1

HY5DS283222BF-5 数据手册

1HY5DS283222BF(P)

PIN DESCRIPTION

TYPE

DESCRIPTION

Clock: CK and /CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of /CK. Output

(read) data is referenced to the crossings of CK and /CK (both directions of crossing).

CK, /CK

Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF

REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE

must be maintained high throughout READ and WRITE accesses. Input buffers, excluding

CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are

disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW

level after Vdd is applied.

CKE

Input

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-

mands are masked when CS is registered high. CS provides for external bank selection on

systems with multiple banks. CS is considered part of the command code.

/CS

Input

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-

CHARGE command is being applied.

BA0, BA1

Address Inputs: Provide the row address for ACTIVE commands, and the column address

and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A8 is sampled during a precharge command to

determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8

HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The

address inputs also provide the op code during a MODE REGISTER SET command. BA0

and BA1 define which mode register is loaded during the MODE REGISTER SET command

(MRS or EMRS).

A0 ~ A11

Input

Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being

entered.

/RAS, /CAS, /WE

DM0 ~ DM3

Input

Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-

pled on both edges of DQS. Although DM pins are input only, the DM loading matches the

DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the

data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the

data on DQ24-Q31.

Data Strobe: Output with read data, input with write data. Edge aligned with read data,

centered in write data. Used to capture write data. DQS0 corresponds to the data on

DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on

DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31

D Q S 0 ~ D Q S 3

I / O

DQ0 ~ DQ31

VDD/VSS

VDDQ/VSSQ

VREF

I/O

Data input / output pin : Data Bus

Supply

Power supply for internal circuits and input buffers.

Power supply for output buffers for noise immunity.

Reference voltage for inputs for SSTL interface.

No connection.

Rev. 1.1 / May. 2005

1 2 3 456 7 8...28

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与HY5DS283222BF-5相关器件

型号	品牌	描述	获取价格	数据表
HY5DS283222BFP-28	HYNIX	128M(4Mx32) GDDR SDRAM	获取价格
HY5DS283222BFP-33	HYNIX	128M(4Mx32) GDDR SDRAM	获取价格
HY5DS283222BFP-36	HYNIX	128M(4Mx32) GDDR SDRAM	获取价格
HY5DS283222BFP-4	HYNIX	128M(4Mx32) GDDR SDRAM	获取价格
HY5DS283222BFP-5	HYNIX	DDR DRAM, 4MX32, 0.6ns, CMOS, PBGA144, 12 X 12 MM, LEAD FREE, FBGA-144	获取价格
HY5DS573222F	HYNIX	256M(8Mx32) GDDR SDRAM	获取价格

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