Datasheet > HY5DS113222FMP-4

HY5DS113222FMP-4

更新时间： 2022-11-24 21:08:36

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器双倍数据速率
页数	文件大小	规格书
30页	432K
描述
512M(16Mx32) GDDR SDRAM

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数据手册

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HY5DS113222FMP-4 数据手册

HY5DS113222FM(P)

SIMPLIFIED COMMAND TRUTH TABLE

CS0/

CS1

A8/

Command

CKEn-1

CKEn

RAS

CAS

ADDR

Note

Extended Mode Register Set

Mode Register Set

Device Deselect

No Operation

OP code

1,2,6

Bank Active

1,7

1,3,7

1,7

1,4,7

1,5

Read

Read with Autoprecharge

Write

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Read Burst Stop

Auto Refresh

Entry

1,6

Self Refresh

Exit

1,6

Entry

Precharge Power

Down Mode

Exit

Entry

Active Power

Down Mode

Exit

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

Note :

1. DM(0~3) states are Don’t Care. Refer to below Write Mask Truth Table.

2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.

Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP

period from Prechagre command.

3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+tRP).

4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time

(tWR) is needed to guarantee that the last data has been completely written.

5. If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be

precharged.

6. Both of CS0 & CS1 should be enabled simultaneously.

Rev. 0.1 / Oct. 2004

1...4 5 678 9 10...30

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