HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Document Title
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
Revision History
No.
0.0
History
Draft Date
Remark
1) Initial Draft
Nov. 28. 2003 Preliminary
Mar. 11. 2004 Preliminary
0.1
1) Add 1.8V Operation Product to Data sheet
1) Change AC Characteristics
- tWP(25ns->40ns), tWC(50ns->60ns),
- tRP(30ns->40ns), tRC(50ns->60ns),
- tREADID(35ns->45ns)
0.2
Apr. 29. 2004 Preliminary
1) Add Errata (3V Product)
tWH tREH
Specification
Relaxed value
15
20
15
20
0.3
May. 14. 2004 Preliminary
2) Add Applicaiton Note
Reset command must be issued when the controller writes data to
another 512Mb.(i.e. When A26 is changed during program.)
3) Modify the description of Device Operations
- /CE Don’t Care Enabled(Disabled) -> Sequential Row Read Disabled
(Enabled) (Page22)
4) Add the description of System Interface Using /CE don’t care (Page37)
1) Delete Errata
2) Change Characteristics
tCRY
tREA@ID Read
0.4
0.5
Jun. 01. 2004 Preliminary
Before
After
60 + tr
70 + tr
35
45
3) Delete Cache Program
1) Change TSOP1, WSOP1, FBGA package dimension
2) Edit TSOP1, WSOP1 package figures
3) Change FBGA package figure
Oct. 20. 2004
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.5 / Oct. 2004
1