Datasheet > HXR5104B

HXR5104B

更新时间： 2024-02-13 02:29:05

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	171K
描述
4 Channel 14Gbps Receiver

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中文翻译

获取价格

数据手册

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HXR5104B 数据手册

IDT70V9389/289L

High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM

Industrial & Commercial Temperature Ranges

PinNames

Left Port

Right Port

CE0R, CE1R

R/W

0R - A15R

I/O0R - I/O17R

CLK

Names

Chip Enables⁽³⁾

CE^0L,CE1L

R/W

0L - A15L

I/O0L - I/O17L

CLK

Read/Write Enable

Output Enable

Address

(1)

Data Input/Output

Clock

Upper Byte Select⁽²⁾

Lower Byte Select⁽²⁾

Address Strobe Enable

Counter Enable

Counter Reset

ADS

CNTEN

CNTRST

FT/PIPE

ADS

CNTEN

CNTRST

FT/PIPE

Flow-Through / Pipeline

Power (3.3V)

NOTES:

1. I/O0X - I/O15X for IDT70V9289.

2. LB and UB are single buffered regardless of state of FT/PIPE.

3. CEo and CE1 are single buffered when FT/PIPE = VIL,

CEo and CE1 are double buffered when FT/PIPE = VIH,

i.e. the signals take two cycles to deselect.

Ground (0V)

4856 tbl 01

Truth Table I—Read/Write and Enable Control^(1,2,3)

Upper Byte

Lower Byte

MODE

(5)

(6)

(7)

(5)

UB⁽⁴⁾

LB⁽⁴⁾

CLK

R/W

I/O9-17

I/O^0-8

↑

High-Z

DATA^IN

DATAIN

High-Z

DATAOUT

High-Z

Deselected–Power Down

Both Bytes Deselected

Write to Upper Byte Only

Write to Lower Byte Only

Write to Both Bytes

↑

DIN

↑

High-Z

DATAIN

DATA^OUT

High-Z

↑

Read Upper Byte Only

Read Lower Byte Only

Read Both Bytes

↑

DATA^OUT

High-Z

Outputs Disabled

4856 tbl 02

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = X.

3. OE is an asynchronous input signal.

4. LB and UB are single buffered regardless of state of FT/PIPE.

5. CEo and CE1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.

6. I/O8 - I/O15 for IDT70V9289.

7. I/O0 - I/O7 for IDT70V9289.

6.462

1...3 4 567 8 9...19

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