HV9605X

更新时间： 2024-02-07 13:14:51

品牌	Logo	应用领域
超科 - SUPERTEX		稳压器开关式稳压器或控制器电源电路开关式控制器综合业务数字网信息通信管理
页数	文件大小	规格书
5页	37K
描述
High Voltage Current Mode PWM Controller for ISDN Equipment

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技术参数
数据手册

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HV9605X 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	DIE
包装说明：	DIE,	针数：	14
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.91
Is Samacsys：	N	模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	CURRENT-MODE	控制技术：	PULSE WIDTH MODULATION
最大输入电压：	8 V	最小输入电压：	4.7 V
标称输入电压：	5 V	JESD-30 代码：	X-XUUC-N14
JESD-609代码：	e0	功能数量：	1
端子数量：	14	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	DIE	封装形状：	UNSPECIFIED
封装形式：	UNCASED CHIP	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	表面贴装：	YES
切换器配置：	SINGLE	技术：	BICMOS
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	NO LEAD	端子位置：	UPPER
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

HV9605X 数据手册

HV9605

Pin Description

SGND - Common connection for all low level signal and digital

circuits. While SGND and PGND must be electrically connected

together, having separate common pins enhances the ability of

the designer to prevent coupling of noise into critical circuits.

COMP - The low impedance output of the error amplifier.

- Thehighimpedanceinvertinginputoftheerroramplifier.

- The high impedance non-inverting input of the error

amplifier.

PGND - This pin provides common return for the high transient

current of the output driver circuits. While PGND and SGND must

be electrically connected, having a separate connection prevents

commonnoisecreatedbythehightransientcurrentsoftheoutput

driver from being injected into critical circuits.

REF

- This pin provides a 2% accuracy 1.20V low output

impedancebufferedreferencewhichiscurrentlimitedto0.5mAmps

and should be bypassed, REF to SGND, with a 0.1µF ceramic

capacitor.

- The resistor connected from this pin to SGND sets the

+V_IN

- Thisisthestart-uplinearpre-regulatorinputwhichcan

frequency of the internal oscillator by setting the charging current

for the internal timing capacitor. The oscillator frequency is twice

the PWM output frequency.

accept DC input voltages in the range of 15V to 250V. With

START and STOP set to more than 20V, the leakage current on

this pin is less than 6.0µA at +V_IN= 20V.

STATUS - This output is held low until the +V_INvoltage reaches

the programmed START voltage. It remains low until the boot-

strap supply to V_DDforces the voltage above the internal regulator

set point. It is further held low while the control amplifier output on

the COMP pin is forced to its high limit by a low output from the

converter. Once all these conditions are satisfied, this output will

rise to V_DDwith a time constant set by the external capacitor

indicating that normal operation has been reached. This output

may be used to control the reset of a microprocessor.

START - The resistive divider from +V_INsets the start voltage.

STOP - The resistive divider from +V_INsets the stop voltage.

V_DD

- This is the supply pin for the PWM circuits. When the

input voltage to the +V_INpin exceeds the start voltage the input

regulator seeks to regulate the voltage on the capacitor con-

nected to this pin to a nominal 4.5V.

OUT

- This high current push-pull CMOS output is intended

to drive the gate of a power MOSFET. In order to protect the

power MOSFET in high electrical noise environment, this output

appears as low impedance to PGND when V_DDis at zero volts.

- This is the current sense input to the PWM compara-

tors. Under normal operation the over current limit is triggered

when the voltage on this pin is at 0.70V and the loop control

operatingpeakcurrentmaybesettoanylevelbelowthis, typically

in the range of 0.2 to 0.5V.

Pin Configuration

+V_IN

STOP

START

REF

COMP

STATUS

V_DD

PGND

SGND

OUT

14 Pin SOIC/DIP Package

11/30/98

1 2 345

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