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HV62106XW PDF预览

HV62106XW

更新时间: 2024-09-26 03:43:07
品牌 Logo 应用领域
超科 - SUPERTEX 显示驱动器驱动程序和接口接口集成电路
页数 文件大小 规格书
5页 37K
描述
64-Channel Gray-Shade Display Column Driver

HV62106XW 技术参数

生命周期:Obsolete包装说明:DIE,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
数据输入模式:PARALLEL显示模式:DOT MATRIX
接口集成电路类型:EL DISPLAY DRIVERJESD-30 代码:X-XUUC-N105
复用显示功能:NO功能数量:1
区段数:64端子数量:105
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:UNSPECIFIED封装形式:UNCASED CHIP
认证状态:Not Qualified表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:NO LEAD端子位置:UPPER
最小 fmax:7 MHzBase Number Matches:1

HV62106XW 数据手册

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HV62106  
64-Channel Gray-Shade Display Column Driver  
Ordering Information  
Package Options*  
Device  
Die in wafer form  
Die in waffle pack  
HV62106  
HV62106XW  
HV62106X  
*Consult factory for availability of bumped die.  
General Description  
Features  
Not recommended for new designs.  
5V CMOS inputs  
64 outputs per device  
TheHV62106isa64-channelcolumndriverICdesignedforgray  
shade flat panel displays. Using Supertex’s unique HVCMOS®  
technology, it is capable of providing gray shading by pulse width  
modulation (PWM) conversion.  
Up to 60V output voltage  
Capable of 4 output pulse widths  
PWM gray shade conversion  
Two 2-bit data buses  
A high level on the chip select input enables the IC to load data  
into a set of input data latches. This input data, in two groups of  
two, are latched into the input data latches on both edges of the  
Shift Clock. The data stored in these input data latches is  
transferred to a set of output data latches on the rising edge of  
Load Count. After the input data registers are full, a chip select  
output signal is provided for enabling the next IC in the chain.  
28 MHz data throughput rate  
Pin-programmable shift direction (DIR)  
Integrated high-voltage CMOS technology  
Optimized layout for COG use  
12  
A master binary counter is reset with a high level on Load Count  
and is incremented on the rising edge of Count Clock. The data  
stored in the output data latches is compared to the contents of  
the master counter. The output of the comparator drives the high  
voltage output devices. The higher the binary number in the  
output data latches, the longer the pulse width will be on the  
corresponding output.  
DIR is a shift-direction-select input which is provided to inter-  
change the direction of the latched data inputs. When the DIR  
input is high, CS2 becomes chip select input and data is latched  
into the data latches in the sequence of HVOUT1 to HVOUT64.  
When the DIR input is low, CS1 becomes chip select input and  
data is latched into the data latches in the sequence of HVOUT64  
to HVOUT1. DIN1 and DIN2 load in data for odd number of outputs.  
DIN3 and DIN4 load in data for even number of outputs.  
Absolute Maximum Ratings  
Supply voltage, VDD  
-0.5V to +7.5V  
Supply voltage, VPP  
-0.5V to +70V  
-0.5V to VDD + 0.5V  
-40°C to +85°C  
Logic input levels  
Operating temperature range  
Storage temperature range  
-65°C to +150°C  
Note:  
All voltages are referenced to GND.  
12-111  

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