HV506
Preliminary
275V 40-Channel Row Driver with SCR Outputs
Ordering Information
Package Options
Device
80-Lead
Ceramic Gullwing
64-Lead 3-Sided
Plastic Gullwing
Die
HV506
HV506DG
HV506PG
HV506X
Features
General Description
The HV506 is a low-voltage serial to high-voltage parallel con-
verter with push-pull outputs. It is especially suitable for use as
a symmetric row driver in AC thin-film electroluminescent
(ACTFEL) displays.
❏ Processed with HVDI technology
❏ Symmetric row drive
❏ Output voltage up to 275V
❏ Source/Sink current 300mA (min.)
❏ Shift Register Speed 3MHz
❏ Pin-programmable shift direction (DIR)
❏ Hi-Rel processing available
When the data reset pin (DRIO) is at logic high, it will reset all the
outputs of the internal shift register to zero.At the same time, the
output of the shift register will start shifting a logic high from the
least significant bit to the most significant bit. The DRIO can be
triggered at any time. The DIR pin controls the direction of data
through the device. When DIR is at logic high, DRIOA is the input
and DRIOB is the output. When DIR is grounded, DRIOB is the input
and the DRIOA is the output. See the Output Sequence Operation
Table for output sequence. The POL and OE pins perform the
polarity select and output enable function respectively. Data is
clocked through the shift register loaded on the low to high
transition of the clock. A logic high in the shift register will cause
the other corresponding output to swing to VDD if POL is high, or
to VSS if POL is low. All other outputs will be in the High-Z state.
If OE is at logic high all outputs will be in the High-Z state. An
output in the High-Z state may block up to 275V above VSS or
275V below VDD. The DP/DN pins are for the positive/negative
discharge of the high voltage output HVOUT. Data output buffers
are provided for cascading devices.
Absolute Maximum Ratings
1
Logic supply voltage, LVDD
Output supply voltage, VDD
-0.5V to +15V
1
-0.5V to +15V
See Note 3
Substrate bias voltage, Vsub
Output voltage, HVOUT
Logic input levels
Continuous total power dissipation2 Ceramic
Plastic
±300V
LVDD requires low current for the HV506 logic section. VDD
requires high current for the output section . Typically these two
pins are at the same potential. The same current and potential
conditionsapplytotheLVSS, logic, andVSS, outputpins. Vsub must
always be equal or greater than the most positive supply.
-0.5V to VDD +0.5V
1900mW
1200mW
Operating temperature range
Plastic
-40°C to +85°C
Ceramic -55°C to +125°C
-65°C to +150°C
260°C
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
Notes:
1. All voltages are referenced to VSS
.
2. For operation above 25°C ambient derate linearly to maximum operating
temperture at 20mW/°C for plasitc and at 19mW/°C for ceramic.
3. Vsub must be the most positive with respect to VSS
.
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
1
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.