HT82J30R/HT82J30A
16 Channel A/D MCU with SPI Interface
Technical Document
·
Tools Information
·
FAQs
·
Application Note
Features
·
·
Operating voltage:
6-level subroutine nesting
f
SYS=4MHz: 2.2V~5.5V crystal clock mode
·
16 channel 8-bit resolution A/D converter
·
·
·
·
fSYS=12MHz: 2.7V~3.7V RC clock mode
35 bidirectional I/O lines (max.)
·
1 channel (6+2)-bit PWM output shared with an I/O
line
·
2 interrupt inputs shared with I/O lines
Bit manipulation instruction
·
8-bit programmable timer/event counter with overflow
interrupt and 7-stage prescaler
15-bit table read instruction
63 powerful instructions
·
·
·
·
·
·
·
·
·
On-chip crystal and RC oscillator
Watchdog Timer
LVR reset voltage of 3V±0.3V
All instructions executed in one or two machine
cycles
4096´15 program memory ROM
216´8 data memory RAM
·
PB2, PB3, PD4, PD7 can be optioned as either
CMOS or NMOS outputs
PFD function for sound generation
·
·
Integrated dual SPI interfaces
HALT function and wake-up feature reduces power
consumption
28-pin SKDIP/SOP and 44-pin QFP packages
·
Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
General Description
The HT82J30R/HT82J30A are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for A/D applications that interface directly to
analog signals, such as those from sensors.
interfaces, Power Down and wake-up functions, en-
hance the versatility of these devices to suit a wide
range of A/D application possibilities such as sensor
signal processing, motor driving, industrial control, con-
sumer products, subsystem controllers, etc. With the
provision of dual SPI interfaces the devices are espe-
cially suitable for Joystick Encoder applications.
The mask version HT82J30A is fully pin and functionally
compatible with the OTP version HT82J30R device.
The advantages of low power consumption, I/O flexibil-
ity, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, Pulse
Width Modulation function, Watchdog timer, SPI
The HT82J30A is under development and will be avail-
able soon.
Rev. 1.00
1
December 20, 2006