1. Using LF441A amplifier (low power - 741 pinout)
2. Specified offset: 0.5mV max
3. Temperature coefficient of input offset: 10µV/°C max
VOS max (0°C to 70°C) = 0.5mV + (70µV)10
= 1.2mV
V
DD
470
V
REF
(+ 25V MAX)
400
3
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
V
LSB
15
14
13
12
11
10
9
REF
UNIPOLAR MODE
(2-QUADRANT)
V
+
DD
200
74273
CLK
R
F
2
V
OUT
REF
N
I
01
02
–
6
0 TO - V
(1-2 -
A
1
3
I
+
)
Add'l nonlinearity (max.) = 1.2mV x 0.065mV/mV
SP7514/
HS3140
8
7
6
5
SP7514/
7516
R
D0
D1
D2
D3
D4
D5
D6
D7
0S
=
78µV (1/2 LSB @ 16 Bits)
Where: 78µV = 1/2 LSB @ 16 Bits (10V range)
WR
G2A
74273
74LS138
4
3
2
BDSEL
G2B
C
Via the above configuration, the SP7514/HS3140
can be used to divide an analog signal by digital code
(i.e. for digitally controlled gain). The transfer func-
tion is given in Table 2, where the value of each bit is
0or1.Divisionbyall“0”sisundefinedandcausesthe
op amp to saturate.
A
2
MSB
GND
CLK
A
A
1
0
B
A
ADDRESS DECODER
LATCHES
Figure 4. Microprocessor Interface to SP7514/HS3140
ResistorRp canbeadded,thiswillparallelRj decreas-
ing the effective resistance. If Cf is reduced the
bandwidth will be increased and settling time de-
creased. HoweverasystempenaltyforloweringCf is
to increase noise gain. The trade-off is noise vs.
settling time. If Rp is added then a large value (1µF or
greater) non-polarized capacitor Cp should be added
in series with Rp to eliminate any DC drifts. If settling
time is not important, eliminate Rp and Cp, and adjust
Cf to prevent overshoot.
Applications Information
Unipolar Operation
Figure 2 shows the interconnections for unipolar
operation. ConnectIO1 andFB1 asshownindiagram.
TieIO2 (Pin7),FB3 (Pin3),andFB4 (Pin1)toGround
(Pin8).Asshown,aseriesresistorisrecommendedin
the VDD supply line to limit current during ‘turn-on’.
To maintain specified linearity, external amplifiers
must be zeroed. Apply an ALL “ZEROES” digital
input and adjust ROS for VOUT = 0 ± 1mV. The
SP7514 and HS3140 have been used successfully
with OP-07, OP-27 and LF441A. For high speed
applications the SP2525 is recommended.
Output Offset
Inmostapplications,theoutputoftheDACisfedinto
an amplifier to convert the DAC’s current output to
voltage. A little known and not commonly discussed
parameteristhelinearityerrorversusoffsetvoltageof
theoutputamplifier. AllCMOSDAC’smustoperate
into a virtual ground, i.e., the summing junction of an
opamp.Anyamplifier’soffsetfromtheamplifierwill
appear as an error at the output (which can be related
to LSB’s of error).
Bipolar Operation
Figure 3 shows the interconnections for bipolar op-
eration. Connect IO1, IO2, FB1, FB3, FB4 as shown in
diagram.TieLDTRtoIO2.Asshown,aseriesresistor
isrecommendedintheVDDsupplylinetolimitcurrent
during‘turn-on.Tomaintainspecifiedlinearity,exter-
nal amplifiers must be zeroed. This is best done with
MostallCMOSDAC’scurrentlyavailableareimple-
mented using an R-2R ladder network. The formula
for nonlinearity is typically 0.67mV/mVOS (not de-
rived here). However the SP7516 has a coefficient of
only 0.065mV/mVOS. This is due to the decoding
technique described earlier. CMOS DAC applica-
tions notes (including this one) always show a poten-
tiometer used to null out the amplifier’s offset. If an
amplifierischosenhaving‘pretrimmed’offsetitmay
bepossibletoeliminatethiscomponent.Considerthe
following calculations:
V
REF set to zero and, the DAC register loaded with
10...0 (MSB = 1). Set R0S1 for V01 = 0. Set R0S2 for
OUT = 0. Set VREF to +10V and adjust RB for VOUT
V
to be 0V.
Grounding
Connect all GND pins to system analog ground
and tie this to digital ground. All unused input pins
must be grounded.
HS3140/SP7514
HS3140/SP7514 14-Bit Multiplying DACs
© Copyright 2000 Sipex Corporation
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