5秒后页面跳转
捷配首页

Datasheet > HS-83C55RH
HS-83C55RH PDF预览

HS-83C55RH

更新时间： 2024-01-08 14:43:22
品牌 Logo 应用领域
英特矽尔 - INTERSIL 内存集成电路有原始数据的样本ROM
页数 文件大小 规格书
12页 698K
描述
Radiation Hardened 16K Bit CMOS ROM

阅读下载

中文翻译

获取价格

HS-83C55RH 数据手册

 浏览型号HS-83C55RH的Datasheet PDF文件第2页浏览型号HS-83C55RH的Datasheet PDF文件第3页浏览型号HS-83C55RH的Datasheet PDF文件第4页浏览型号HS-83C55RH的Datasheet PDF文件第5页浏览型号HS-83C55RH的Datasheet PDF文件第6页浏览型号HS-83C55RH的Datasheet PDF文件第7页 
®
HS-83C55RH  
Radiation Hardened  
16K Bit CMOS ROM  
September 1997  
Features  
t  
HS-83C55RH 40 LEAD BRAZE SEAL DIP  
COMPLIANT OUTLINE D5, CONFIGURATION 3  
TOP VIEW  
• Radiation Hardened EPI-CM
5
- Total Dose 1 x 10 RAD(Si
8
- Transient Upset > 1 x 10 R
12  
- Latch-Up Free > 1 x 10 RA
CE1  
CE2  
1
2
VDD  
PB7  
40  
39  
• 2048 Words x 8 Bits ROM  
• Electrically Equivalent to Sandia 002  
• Pin Compatible with Intel 8355  
• Bus Compatible with HS-80C85RH  
• Single 5 Volt Power Supply  
3
CLK  
38 PB6  
RESET  
4
37  
36  
35  
34  
33  
PB5  
NC  
5
PB4  
PB3  
READY  
6
• Low Standby Current 100µA Max  
• Low Operating Current 2mA/MHz  
• Completely Static Design  
IO/M  
IOR  
7
PB2  
PB1  
8
RD  
IOW  
ALE  
AD0  
• Internal Address Latches  
9
32 PB0  
31 PA7  
• Two General Purpose 8-Bit I/O Ports  
• Multiplexed Address and Data Bus  
• Self Aligned Junction Isolated (SAJI) Process  
10  
11  
12  
PA6  
30  
29  
PA5  
PA4  
PA3  
PA2  
PA1  
PA0  
o
o
• Military Temperature Range -55 C to +125 C  
AD1  
AD2  
AD3  
13  
14  
28  
27  
26  
25  
24  
23  
22  
21  
Description  
15  
16  
17  
18  
19  
20  
The HS-83C55RH is a radiation hardened ROM and I/O chip fabricated  
using the Intersil radiation hardened Self-Aligned Junction Isolated  
(SAJI) silicon gate technology. Latch-up free operation is achieved by  
the use of epitaxial starting material to eliminate the parasitic SCR effect  
seen in conventional bulk CMOS devices.  
AD4  
AD5  
AD6  
AD7  
GND  
A10  
A9  
The HS-83C55RH is intended for use with the HS-80C85RH radiation  
hardened microprocessor system.  
A8  
The ROM portion is designed as 16,384 mask programmable cells orga-  
nized in a 2048 word x 8-bit format. A maximum post irradiation access  
time of 340ns allows the HS-83C55RH to be used with the HS-80C85RH  
CPU without any wait states. This ROM is designed for operation utilizing  
a single 5 volt power supply.  
Block Diagram  
CLK  
READY  
AD0-7  
A8-10  
PORT A  
CE2  
CE1  
(8)  
A
PA0-7  
PB0-7  
2K X 8  
IO/M  
ROM  
ALE  
RD  
PORT B  
(8)  
B
IOW  
RESET  
IOR  
VDD  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
File Number 3045.2  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
11-1  
1234567...12

中文翻译

下载PDF

与HS-83C55RH相关器件

型号 品牌 获取价格 描述 数据表
HS-83C55RH-Q RENESAS

获取价格

 		2KX8 MASK PROM, 340ns, CDIP40
HS84003100J0G AMPHENOL

获取价格

 		Barrier Strip Terminal Block
HS8422T2TASS600 ETC

获取价格

 		ENTERPRISE SOLID-STATE DRIVES
HS8422T80ASS600 ETC

获取价格

 		ENTERPRISE SOLID-STATE DRIVES
HS84302100J0G AMPHENOL

获取价格

 		Barrier Strip Terminal Block
HS84303100J0G AMPHENOL

获取价格

 		Barrier Strip Terminal Block
HS84305000J0G AMPHENOL

获取价格

 		Barrier Strip Terminal Block
HS84305100J0G AMPHENOL

获取价格

 		Barrier Strip Terminal Block
HS84308100J0G AMPHENOL

获取价格

 		Barrier Strip Terminal Block
HS85020-A04 FOXCONN

获取价格

 		Board Connector, 2 Contact(s), 1 Row(s), Male, Right Angle, Surface Mount Terminal, Plug

与HS-83C55RH相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证