Datasheet > HMC625BLP5ETR

HMC625BLP5ETR

更新时间： 2024-02-25 04:07:58

品牌	Logo	应用领域
亚德诺 - ADI		电信电信集成电路
页数	文件大小	规格书
9页	675K
描述
0.5 dB LSB GaAs MMIC 6-Bit Digital Variable Gain Amplifier, DC - 5 GHz

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

HMC625BLP5ETR 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	HVQCCN,
针数：	32	Reach Compliance Code：	compliant
风险等级：	5.66	JESD-30 代码：	S-PQCC-N32
JESD-609代码：	e3	长度：	5 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
座面最大高度：	1 mm	标称供电电压：	5 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	5 mm	Base Number Matches：	1

HMC625BLP5ETR 数据手册

HMC625BLP5E

v02.0616

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL

VARIABLE GAIN AMPLIFIER, DC - 5 GHz

Serial Control Interface

The HMC625BLP5E contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). It is activated when P/S

is kept high. The 6-bit serial word must be loaded MSB ﬁrst. The positive-edge sensitive CLK and LE requires

clean transitions. If mechanical switches were used, sufficient debouncing should be provided. When LE is high,

6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data

transition during output loading.

When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and serial input register is loaded

asynchronously with parallel digital inputs (D0-D5). When LE is high, 6-bit parallel data is transferred to the attenuator.

For all modes of operations, the DVGA state will stay constant while LE is kept low.

Parameter

Typ.

Timing Diagram (Latched Parallel Mode)

Min. serial period, t_SCK

Control set-up time, t_CS

Control hold-time, t_CH

LE setup-time, t_LN

100 ns

20 ns

10 ns

630 ns

Min. LE pulse width, t_LEW

Min LE pulse spacing, t_LES

Serial clock hold-time from LE, t_CKN10 ns

Hold Time t_PH

0 ns

10 ns

2 ns

Latch Enable Minimum width, t_LEN

Setup Time, t_PS

Parallel Mode (Direct Parallel Mode & Latched Parallel Mode)

Note: The parallel mode is enabled when P/S is set to low.

Direct Parallel Mode - The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable)

must be at a logic high to control the attenuator in this manner.

Latched Parallel Mode - The attenuation state is selected using the Control Voltage Inputs and set while the LE is in

the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired

states the LE is pulsed. See timing diagram above for reference.

For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106

Phone: 781-329-4700 • Order online at www.analog.com

Application Support: Phone: 1-800-ANALOG-D

1 2 345 6 7...9

下载PDF

与HMC625BLP5ETR相关器件

型号	品牌	描述	获取价格	数据表
HMC625HFLP5E	HITTITE	0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 6 GHz	获取价格
HMC625LP5	HITTITE	0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, DC - 6 GHz	获取价格
HMC625LP5_10	HITTITE	0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, DC - 6 GHz	获取价格
HMC625LP5E	HITTITE	0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, DC - 6 GHz	获取价格
HMC625LP5ETR	HITTITE	Telecom Circuit, 1-Func, PQCC32, ROHS COMPLIANT, PLASTIC, QFN-32	获取价格
HMC625LP5TR	HITTITE	Telecom Circuit, 1-Func, PQCC32, PLASTIC, QFN-32	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

HMC625BLP5ETR

HMC625BLP5ETR 技术参数

HMC625BLP5ETR 数据手册

与HMC625BLP5ETR相关器件

与HMC625BLP5ETR相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HMC625BLP5ETR

HMC625BLP5ETR 技术参数

HMC625BLP5ETR 数据手册

与HMC625BLP5ETR相关器件

与HMC625BLP5ETR相关文章

您还可以找

您在本页遇到什么问题？