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HMC625BLP5E

更新时间： 2024-01-24 05:05:15
品牌 Logo 应用领域
亚德诺 - ADI 电信电信集成电路
页数 文件大小 规格书
10页 568K
描述
0.5 dB LSB GaAs MMIC 6-Bit Digital Variable Gain Amplifier, DC - 5 GHz

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HMC625BLP5E 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN,
针数：32Reach Compliance Code：compliant
风险等级：1.64Samacsys Description：ANALOG DEVICES - HMC625BLP5E - VAR GAIN AMP, 6BIT, DC-5GHZ, 18DB, QFN32
JESD-30 代码：S-PQCC-N32JESD-609代码：e3
长度：5 mm湿度敏感等级：3
功能数量：1端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260座面最大高度：1 mm
标称供电电压：5 V表面贴装：YES
电信集成电路类型：TELECOM CIRCUIT温度等级：INDUSTRIAL
端子面层：Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：5 mm
Base Number Matches：1

HMC625BLP5E 数据手册

 浏览型号HMC625BLP5E的Datasheet PDF文件第3页浏览型号HMC625BLP5E的Datasheet PDF文件第4页浏览型号HMC625BLP5E的Datasheet PDF文件第5页浏览型号HMC625BLP5E的Datasheet PDF文件第7页浏览型号HMC625BLP5E的Datasheet PDF文件第8页浏览型号HMC625BLP5E的Datasheet PDF文件第9页 
HMC625BLP5E  
v02.0616  
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL  
VARIABLE GAIN AMPLIFIER, DC - 5 GHz  
PUP Truth Table  
Power-Up States  
If LE is set to logic LOW at power-up, the logic state of  
PUP1 and PUP2 determines the power-up state of the  
part per PUP truth table. If the LE is set to logic HIGH  
at power-up, the logic state of D0-D5 determines the  
power-up state of the part per truth table. The DVGA  
latches in the desired power-up state approximately  
200 ms after power-up.  
Gain Relative to Maximum  
LE  
PUP1  
PUP2  
Gain  
0
0
0
0
1
0
1
0
1
X
0
0
1
1
X
-31.5  
-24  
-16  
Insertion Loss  
0 to -31.5 dB  
Note: The logic state of D0 - D5 determines the  
power-up state per truth table shown below when LE  
is high at power-up.  
Power-On Sequence  
The ideal power-up sequence is: GND, Vdd, digital  
inputs, RF inputs. The relative order of the digital  
inputs are not important as long as they are powered  
after Vdd / GND  
Truth Table  
Absolute Maximum Ratings  
RF Input Power [1]  
11.5 dBm (T = +85 °C)  
Control Voltage Input  
Gain  
Relative to  
Maximum  
Gain  
Digital Inputs (Reset, Shift Clock,  
Latch Enable & Serial Input)  
-0.5 to Vdd +0.5V  
D5  
D4  
D3  
D2  
D1  
D0  
Bias Voltage (Vdd)  
5.6V  
High  
High  
High  
High  
High  
High  
Low  
High  
High  
High  
High  
High  
Low  
High  
High  
High  
High  
Low  
High  
High  
High  
Low  
High  
High  
Low  
High  
Low  
0 dB  
-0.5 dB  
-1 dB  
Collector Bias Voltage (Vcc)  
Channel Temperature  
5.5V  
150 °C  
High  
High  
High  
High  
High  
Low  
Continuous Pdiss (T = 85 °C)  
(derate 8.4 mW/°C above 85 °C) [2]  
High  
High  
High  
High  
Low  
-2 dB  
0.546 W  
High  
High  
High  
Low  
-4 dB  
Thermal Resistance [3]  
Storage Temperature  
Operating Temperature  
ESD Sensitivity (HBM)  
119 °C/W  
High  
High  
Low  
-8 dB  
-65 to +150 °C  
-40 to +85 °C  
Class 1A  
High  
Low  
-16 dB  
-31.5 dB  
Low  
Any combination of the above states will provide a reduction in  
gain approximately equal to the sum of the bits selected.  
[1] The maximum RF input power increases by the same amount  
the gain is reduced. The maximum input power at any state is no  
more than 28 dBm.  
Control Voltage Table  
[2] This value is the total power dissipation in the amplifier.  
[3] This is the thermal resistance for the amplifier.  
State  
Vdd = +3V  
Vdd = +5V  
Low  
0 to 0.5V @ <1 µA  
2 to 3V @ <1 µA  
0 to 0.8V @ <1 µA  
2 to 5V @ <1 µA  
High  
ELECTROSTATIC SENSITIVE DEVICE  
OBSERVE HANDLING PRECAUTIONS  
Bias Voltage  
Vdd (V)  
Idd (Typ.) (mA)  
5V  
2.5  
Is (Typ.) (mA)  
85  
Vs (V)  
5V  
For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106  
Phone: 781-329-4700 • Order online at www.analog.com  
5
Application Support: Phone: 1-800-ANALOG-D  
1...345678910

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