Datasheet > HMA510JC-55

HMA510JC-55

更新时间： 2024-02-19 10:09:32

品牌	Logo	应用领域
英特矽尔 - INTERSIL		外围集成电路输入元件
页数	文件大小	规格书
10页	134K
描述
16 x 16-Bit CMOS Parallel Multiplier Accumulator

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HMA510JC-55 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	QCCJ, LDCC68,1.0SQ	Reach Compliance Code：	unknown
风险等级：	5.72	其他特性：	2 X 16 BIT DATA INPUT BUS; ICC SPECIFIED @ 1MHZ
边界扫描：	NO	外部数据总线宽度：	16
JESD-30 代码：	S-PQCC-J68	JESD-609代码：	e0
低功率模式：	NO	端子数量：	68
最高工作温度：	70 °C	最低工作温度：
输出数据总线宽度：	35	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC68,1.0SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
电源：	5 V	认证状态：	Not Qualified
子类别：	DSP Peripherals	最大压摆率：	7 mA
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
uPs/uCs/外围集成电路类型：	DSP PERIPHERAL, MULTIPLIER ACCUMULATOR/SUMMER	Base Number Matches：	1

HMA510JC-55 数据手册

HMA510

Functional Description

The HMA510 is a high speed 16 x 16-bit multiplier accumu-

lator (MAC). It consists of a 16-bit parallel multiplier follower

by a 35-bit accumulator. All inputs and outputs are regis-

tered and are latched on the rising edge of the associated

clock signal. The HMA510 is divided into four sections: the

input section, the multiplier array, the accumulator and the

output/preload section.

TABLE 1. PRELOAD FUNCTION TABLE

OUTPUT REGISTERS

PREL

OEX

OEM

OEL

XTP

MSP

LSP

The input section has two 16-bit Operand Input Registers for

the X and Y operands which are latched on the rising edge

of CLKX and CLKY respectively. A four bit Control Register

(TC, RND, ACC, SUB) is also included and is latched from

either of the input clock signals.

The 16 x 16 multiplier array produces the 32-bit product of

the input operands. Two's complement or unsigned magni-

tude operation can be selected by the use of the TC control.

The 32-bit result may also be rounded through the use of the

RND control. In this case, a ‘1’ is added to the MSB of the

LSP (bit P15). The 32-bit product is zero-filled or sign-

extended as appropriate and passed as a 35-bit number to

the accumulator section.

The accumulator functions are controlled by the ACC, SUB

and PREL control inputs. Four functions may be selected:

the accumulator may be loaded with the current product; the

product may be added to the accumulator contents; the

accumulator contents may be subtracted from the current

product; or the accumulator may be loaded from the bidirec-

tional ports. The Accumulator Registers are updated at the

rising edge of the CLKP signal.

= Output Buffers at High Impedance (Disabled).

Q = Output Buffers at LOW Impedance. Contents of Output Reg-

ister Available Through Output Ports.

PL = Output disabled. Preload data supplied to the output pins will

be loaded into the register at the rising edge of CLKP.

The output/preload section contains the Accumulator/Output

trolled by the signals PREL, OEX, OEM and OEL. When

PREL is high, the output buffers are in a high impedance

state. When one of the controls OEX, OEM or OEL are also

high, data present at the outputs will be preloaded into the

associated register on the rising edge of CLKP. When PREL

is low, the signals OEX, OEM and OEL are enable controls

for their respective three-state output ports.

TABLE 2. ACCUMULATOR FUNCTION TABLE

PREL

ACC

SUB

OPERATION

Load

Add

Subtract

Preload

1 2 345 6 7...10

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