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HM628511HLJP-10 PDF预览

HM628511HLJP-10

更新时间: 2024-11-20 20:12:19
品牌 Logo 应用领域
瑞萨 - RENESAS 输入元件静态存储器光电二极管输出元件内存集成电路
页数 文件大小 规格书
14页 112K
描述
512KX8 CACHE SRAM, 10ns, PDSO36, 0.400 INCH, PLASTIC, SOJ-36

HM628511HLJP-10 技术参数

生命周期:Transferred零件包装代码:SOJ
包装说明:SOJ,针数:36
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.77
最长访问时间:10 ns其他特性:TTL COMPATIBLE INPUTS/OUTPUTS
JESD-30 代码:R-PDSO-J36长度:23.25 mm
内存密度:4194304 bit内存集成电路类型:CACHE SRAM
内存宽度:8功能数量:1
端子数量:36字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:3.76 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

HM628511HLJP-10 数据手册

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HM628511H Series  
4M High Speed SRAM (512-kword × 8-bit)  
ADE-203-762D (Z)  
Rev. 1.0  
Sept. 15, 1998  
Description  
The HM628511H Series is a 4-Mbit high speed static RAM organized 512-k word × 8-bit. It has realized  
high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell)and high  
speed circuit designing technology. It is most appropriate for the application which requires high speed,  
high density memory and wide bit width configuration, such as cache and buffer memory in system. It is  
packaged in 400-mil 36-pin plastic SOJ.  
Features  
Single 5.0 V supply : 5.0 V ± 10 %  
Access time 10 /12 /15 ns (max)  
Completely static memory  
No clock or timing strobe required  
Equal access and cycle times  
Directly TTL compatible  
All inputs and outputs  
Operating current : 180 / 160 / 140 mA (max)  
TTL standby current : 70 / 60 / 50 mA (max)  
CMOS standby current : 5 mA (max)  
: 1.2 mA (max) (L-version)  
Data retention current: 0.8 mA (max) (L-version)  
Data retention voltage: 2 V (min) (L-version)  
Center VCC and VSS type pinout  

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