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HI5728INZ PDF预览

HI5728INZ

更新时间: 2024-02-12 19:13:20
品牌 Logo 应用领域
英特矽尔 - INTERSIL 转换器
页数 文件大小 规格书
19页 458K
描述
10-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter

HI5728INZ 技术参数

生命周期:Obsolete零件包装代码:LQFP
包装说明:LFQFP, QFP48,.35SQ,20针数:48
Reach Compliance Code:compliant风险等级:5.73
最大模拟输出电压:1.25 V最小模拟输出电压:-0.3 V
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:PARALLEL, WORDJESD-30 代码:S-PQFP-G48
JESD-609代码:e3长度:7 mm
最大线性误差 (EL):0.0977%湿度敏感等级:4
位数:10功能数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP48,.35SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
标称安定时间 (tstl):35 µs子类别:Other Converters
最大压摆率:60 mA标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

HI5728INZ 数据手册

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HI5728  
Pin Descriptions  
PIN NO.  
PIN NAME  
PIN DESCRIPTION  
39, 38, 37, 36, QD9 (MSB) Through Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q  
35, 34, 33, 32,  
31, 30  
QD0 (LSB)  
channel.  
1, 2, 3, 4, 5, 6, 7, ID9 (MSB) Through Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I  
46, 47, 48  
ID0 (LSB)  
channel.  
8
SLEEP  
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep  
pin has internal 20µA active pull-down current.  
15  
23  
REFLO  
REFIO  
Connect to analog ground to enable internal 1.2V reference or connect to AV  
to disable.  
DD  
Reference voltage input if internal reference is disabled and reference voltage output if internal reference is  
enabled. Use 0.1µF cap to ground when internal reference is enabled.  
22  
FSADJ  
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output  
Current Per Channel = 32 x I  
.
FSADJ  
14, 24  
ICOMP1, QCOMP1 Reduces noise. Connect each to AV  
with 0.1µF capacitor near each pin. The ICOMP1 and QCOMP1  
DD  
pins MUST be tied together externally.  
13, 18, 19, 25  
AGND  
IOUTB  
IOUTA  
QOUTB  
QOUTA  
NC  
Analog Ground Connections.  
17  
The complimentary current output of the I channel. Bits set to all 0s gives full scale current.  
Current output of the I channel. Bits set to all 1s gives full scale current.  
The complimentary current output of the Q channel. Bits set to all 0s gives full scale current.  
Current output of the Q channel. Bits set to all 1s gives full scale current.  
No Connect. Recommended: connect to ground.  
16  
20  
21  
11, 27  
12, 26  
10, 28, 41, 44  
9, 29, 40, 45  
43  
AV  
Analog Supply (+2.7V to +5.5V).  
DD  
DGND  
DV  
Digital Ground.  
Supply voltage for digital circuitry (+2.7V to +5.5V).  
DD  
ICLK  
Clock input for I channel. Positive edge of clock latches data.  
Clock input for Q channel. Positive edge of clock latches data.  
42  
QCLK  
FN4321.5  
January 22, 2010  
5

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