HI-15530CDT

更新时间： 2024-01-31 12:37:00

品牌	Logo	应用领域
HOLTIC		解码器编码器
页数	文件大小	规格书
11页	314K
描述
Manchester Encoder / Decoder

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数据手册

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HI-15530CDT 数据手册

HI-15530

ENCODER OPERATION

The encoder requires a single clock with a frequency of To abort the Encoder transmission a positive pulse must be

twice the desired rate applied at the SEND CLOCK input. applied at MASTER RESET. Anytime after or during this

An auxiliary divide by six counter is provided on chip which pulse, a low to high transition on SEND CLOCK clears the

can be utilized to produce the SEND CLOCK by dividing internal counters and initializes the Encoder for a new

the ENCODER CLOCK.

word.

The Encoder's cycle begins when ENCODER ENABLE is

high during a falling edge of ENCODER SHIFT CLOCK (1).

This cycle lasts for one word length or twenty ENCODER

SHIFT CLOCK periods. At the next low-to-high transition of

the ENCODER SHIFT CLOCK, a high at SYNC SELECT

input actuates a command sync or a low will produce a

data sync for that word (2). When the Encoder is ready to

accept data, the SEND DATA output will go high and

remain high for sixteen ENCODER SHIFT CLOCK periods

(3). During these sixteen periods the data should be

clocked into the SERIAL DATA input with every low-to-high

transition of the ENCODER SHIFT CLOCK (3) - (4). After

the sync and the Manchester II coded data are transmitted

through the BIPOLAR ONE and BIPOLAR ZERO outputs,

the Encoder adds on an additional bit which is the parity for

that word (5). If ENCODER ENABLE is held high continu-

ously, consecutive words will be encoded without an

interframe gap. ENCODER ENABLE must go low by time

(5) as shown to prevent a consecutive word from being

encoded. At any time a low on the OUTPUT INHIBIT input

will force both bipolar outputs to a high state but will not

affect the Encoder in any other way.

MASTER RESET

OUTPUT

INHIBIT

SEND CLK IN

BIPOLAR

ONE OUT

¸ 6 OUT

¸ 2

Character

Former

¸ 6

BIPOLAR

ZERO OUT

ENCODER CLK

Bit

Counter

SYNC

SELECT

SERIAL

DATA

SEND

DATA

ENCODER

SHIFT

CLK

ENCODER

ENABLE

TIMING

SEND CLK

ENCODER

SHIFT CLK

ENCODER

ENABLE

DON’T CARE

SYNC SELECT

SEND DATA

VALID

SERIAL

DATA IN

BIPOLAR

ONE OUT

SYNC

BIPLOAR

ZERO OUT

SYNC

(3)

(1) (2)

(4) (5)

HOLT INTEGRATED CIRCUITS

1 234 5 6 7...11

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