Datasheet > HDD32M72B18RPW-10A

HDD32M72B18RPW-10A

更新时间： 2024-02-10 17:17:40

品牌	Logo	应用领域
HANBIT		动态存储器
页数	文件大小	规格书
12页	154K
描述
DRAM

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技术参数
数据手册

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HDD32M72B18RPW-10A 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.75
Base Number Matches：	1

HDD32M72B18RPW-10A 数据手册

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HANBit

HDD32M72B18RPW

BL = 2, reads, continuous burst

One bank open, Address and control inputs

changing once per clock cycle, I_OUT= 0mA

Operating current

(burst read)

I_DD4R

1839

2055

BL = 2, write, continuous burst

One bank open, Address and control inputs

changing once per clock cycle

Operating current

(Bust write)

I_DD4W

1839

2019

2100

2415

2100

2415

tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,

10*tCK for DDR266A & DDR266B at 133Mhz,

distributed refresh

Auto refresh current

I_DD5

Self

refresh

current

CKE =< 0.2V, External clock should be on

tCK = 100Mhz for DDR200, 133Mhz for DDR266A

& DDR266B

Normal

336

318

336

318

336

318

I_DD6

Low Power

Four bank interleaving with BL=4

-Refer to the following page for detailed test

condition

Operating current

(Four bank operation)

I_DD7A

2919

3315

Notes:

Operation at above absolute maximum rating can adversely affect device reliability

AC OPERATING CONDITIONS

PARAMETER

STMBOL

MIN

MAX

UNIT

NOTE

(AC)

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

Input Differential Voltage, CK and CK inputs

VREF + 0.31

VREF - 0.31

VDDQ+0.6

0.7

Input Crossing Point Voltage, CK and CK inputs

0.5*VDDQ-0.2

0.5*VDDQ+0.2

Notes:

1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of V_IXis expected to equal 0.5* V_DDQof the transmitting device and must track variations in the DC level of

the same

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the

pad in simula-tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited

20MHz.

AC OPERATING TEST CONDITIONS

PARAMETER

Input reference voltage for Clock

VALUE

0.5 * V_DDQ

1.5

UNIT

NOTE

Input signal maximum peak swing

Input signal minimum slew rate

Input Levels(V_IH/V_IL)

1.0

V_REF+0.35/V_REF

V_REF

Input timing measurement reference level

Output timing measurement reference level

Output load condition

V_TT

See Load Circuit

URL : www.hbe.co.kr

REV 1.0 (August.2002)

HANBit Electronics Co.,Ltd.

1...4 5 678 9 10...12

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