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HDD32M72B18RPW-10A PDF预览

HDD32M72B18RPW-10A

更新时间： 2024-02-27 12:25:38
品牌 Logo 应用领域
HANBIT 动态存储器
页数 文件大小 规格书
12页 154K
描述
DRAM

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HDD32M72B18RPW-10A 技术参数

生命周期：Contact Manufacturer包装说明：,
Reach Compliance Code：unknown风险等级：5.75
Base Number Matches：1

HDD32M72B18RPW-10A 数据手册

 浏览型号HDD32M72B18RPW-10A的Datasheet PDF文件第2页浏览型号HDD32M72B18RPW-10A的Datasheet PDF文件第3页浏览型号HDD32M72B18RPW-10A的Datasheet PDF文件第4页浏览型号HDD32M72B18RPW-10A的Datasheet PDF文件第6页浏览型号HDD32M72B18RPW-10A的Datasheet PDF文件第7页浏览型号HDD32M72B18RPW-10A的Datasheet PDF文件第8页 
HANBit  
HDD32M72B18RPW  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
Voltage on any pin relative to Vss  
Voltage on VDD supply relative to Vss  
Voltage on VDDQ supply relative to Vss  
Storage temperature  
SYMBOL  
VIN, VOUT  
VDD  
RATING  
UNTE  
V
-0.5 ~ 3.6  
-1.0 ~ 3.6  
-0.5 ~ 3.6  
-55 ~ +150  
18  
V
VDDQ  
TSTG  
V
°C  
W
Power dissipation  
PD  
Short circuit current  
IOS  
50  
mA  
Notes:  
Operation at above absolute maximum rating can adversely affect device reliability  
DC OPERATING CONDITIONS  
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) )  
PARAMETER  
SYMBOL  
VDD  
MIN  
2.3  
MAX  
2.7  
UNIT  
NOTE  
Supply Voltage  
V
V
V
I/O Supply Voltage  
VDDQ  
2.3  
2.7  
I/O Reference Voltage  
VREF  
VDDQ/2 - 50mA  
VDDQ/2 +  
50mA  
1
I/O Termination Voltage(system)  
Input High Voltage  
VTT  
V
REF – 0.04  
VREF + 0.04  
VREF + 0.3  
VREF - 0.15  
VDDQ + 0.3  
VDDQ + 0.6  
1.35  
V
V
V
V
V
V
2
4
4
VIH (DC)  
VIL (DC)  
VIN (DC)  
VID (DC)  
VIX (DC)  
VREF + 0.15  
-0.3  
Input Low Voltage  
Input Voltage Level, CK and /CK inputs  
Input Differential Voltage, CK and /CK inputs  
Input crossing point Voltage, CK and /CK  
inputs  
-0.3  
0.3  
3
5
1.15  
Input leakage current  
I LI  
I OZ  
I OH  
I OL  
-2  
-5  
2
5
uA  
uA  
Output leakage current  
Output High current (VOUT = 1.95V)  
Output Low current (VOUT = 0.35V)  
-16.8  
16.8  
mA  
mA  
Notes :  
1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC  
offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and  
internal DRAM noise coupled to VREF , both of which may result in VREF noise. VREF should be de-coupled with an  
inductance of £ 3nH.  
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set  
equal to VREF, and must track variations in the DC level of VREF  
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.  
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the  
pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited  
to 200MHZ.  
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of  
the same.  
6. These charactericteristics obey the SSTL-2 class II standards.  
URL : www.hbe.co.kr  
REV 1.0 (August.2002)  
5
HANBit Electronics Co.,Ltd.  
12345678...12

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