Datasheet > HDD32M72B18RPW-10A

HDD32M72B18RPW-10A

更新时间： 2024-01-20 09:25:10

品牌	Logo	应用领域
HANBIT		动态存储器
页数	文件大小	规格书
12页	154K
描述
DRAM

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HDD32M72B18RPW-10A 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.75
Base Number Matches：	1

HDD32M72B18RPW-10A 数据手册

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HANBit

HDD32M72B18RPW

DDR SDRAM Module 256Mbyte (32Mx72bit), based on 16Mx8, 4Banks, 4K

Ref., 184Pin-DIMM with PLL & Register

Part No. HDD32M72D18RPW

GENERAL DESCRIPTION

The HDD32M72D18RPW is a 64M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory

module. The module consists of eighteen CMOS 16M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages

and 2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on

the printed circuit board in parallel for each DDR SDRAM. The HDD32M72D18RPW is a DIMM(Dual in line Memory

Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible

on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device

to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be

powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.

FEATURES

• Part Identification

HDD32M72B18RPW – 10A

HDD32M72B18RPW – 13A

HDD32M72B18RPW – 13B

100MHz (CL=2)

133MHz (CL=2)

133MHz (CL=2.5)

• 256MB(32Mx72) registered DDR DIMM based on 16Mx8 DDR SDRSM

• 2.5V ± 0.2V VDD and VDDQ power supply

• Auto & self refresh capability (4K Cycles / 64ms)

• All input and output are compatible with SSTL_2 interface

• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock

• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock

• MRS cycle with address key programs

- Latency (Access from column address) : 2, 2.5

- Burst length : 2, 4, 8

- Data scramble : Sequential & Interleave

• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock

• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock

• The used device is 4M x 8bit x 4Banks DDR SDRAM

URL : www.hbe.co.kr

REV 1.0 (August.2002)

HANBit Electronics Co.,Ltd.

12 3 4 5 6 7...12

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