Datasheet > HDC3022DEJR

HDC3022DEJR

更新时间： 2022-05-14 22:18:55

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
51页	2002K
描述
HDC302x High-Accuracy, Low-Power, Digital Humidity and Temperature Sensor With Ultra-Low Drift

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HDC3022DEJR 数据手册

HDC3020

SNAS778 – JUNE 2021

www.ti.com

(4) Based on THB (temperature humidity bias) testing. Excludes the impact of dust, gas phase solvents and other contaminents such as

vapors from packaging materials, adhesives, or taptes, etc.

(5) The hysteresis value is the difference between the RH measurement in a rising and falling RH environment, at a specific RH point

(6) Actual response times will vary dependent on system thermal mass and air-flow

(7) Time for the RH output to change by 63% of the total RH change after a step change in environmental humidity

(8) Measurement duration includes the time to measure RH plus Temp

(9) I_{DD_AVG_EQN}= measuruement freq x I_{DD_ACTIVE}x t_meas+ I_sleepx (1- (measurement freq x t_meas))

6.6 Switching Characteristics

T_A= -40°C to 125°C and V_DD= 1.62V to 5.50V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SCL, SDA PINS

f_SCL

SCL clock frequency⁽¹⁾

0.6

1.3

100

MHz

µs

t_HIGH

High period of the SCL clock⁽¹⁾

LOW period of the SCL clock⁽¹⁾

Setup Time: Data⁽¹⁾

t_LOW

µs

t_SU;DAT

t_HD;DAT

t_SU;STA

t_HD;STA

t_SU;STO

t_R;SCL

Hold Time: Data⁽¹⁾

µs

Set-up time: Repeated START condition⁽¹⁾

Hold time: Repeated START condition^{(1) (2)}

Set-up time: STOP condition⁽¹⁾

Rise Time: SCL⁽¹⁾

0.6

µs

300 ns

µs

t_R;SDA

Rise Time: SDA⁽¹⁾

t_F;SCL

Fall Time: SCL⁽¹⁾

20*(V_DD/5.5V)

1.3

t_F;SDA

Fall Time: SDA⁽¹⁾

t_BUF

Bus free time between a STOP and START condition⁽¹⁾

Data valid time^{(1) (3)}

t_VD;DAT

t_VD;ACK

RESET

t_{RESET_NPW}

0.9 µs

Data valid acknowledge time^{(1) (4)}

Negative pulse width to trigger hard reset

µs

EEPROM (T, RH OFFSET)

t_{OS_PROG}

Offset Programming Time

15 ms

(1) Guaranteed by design/characterization; not production tested

(2) After this period, the first clock pulse is generated

(3) Time for data signal from SCL low to SDA output (high to low, depending on which is worse)

(4) Time for acknowledement signal from SCL low to SDA output (high or low, depending on which is worse)

6.7 Timing Diagram

t_LOW

t_R

t_F

t_HIGH

V_IH

SCL

V_IL

t_SU;STO

t_HD;DAT

t_VD;DAT

t_SU;STA

t_HD;STA

t_BUF

t_SU;DAT

V_IH

V_IL

SDA

Figure 6-1. HDC302x I²C Timing Diagram

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