Datasheet > HCTS11MS

HCTS11MS

更新时间： 2024-10-01 22:55:03

品牌	Logo	应用领域
英特矽尔 - INTERSIL		逻辑集成电路栅
页数	文件大小	规格书
7页	124K
描述
Radiation Hardened Triple 3-Input AND Gate

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HCTS11MS 数据手册

HCTS11MS

Radiation Hardened

Triple 3-Input AND Gate

November 1994

Features

Pinouts

14 PIN CERAMIC DUAL-IN-LINE

MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C

TOP VIEW

• 3 Micron Radiation Hardened SOS CMOS

• Total Dose 200K or 1 Mega-RAD (Si)

• Dose Rate Upset >10¹⁰RAD(Si)/s 20ns Pulse

• Latch-Up Free Under Any Conditions

• Military Temperature Range: -55^oC to +125^oC

• Signiﬁcant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

14 VCC

13 C1

12 Y1

11 C3

10 B3

• LSTTL Input Compatibility

- VIL = 0.8V Max.

- VIH = VCC/2 Min

GND

• Input Current Levels Ii ≤ 5µA at VOL, VOH

Description

14 PIN CERAMIC FLAT PACK

MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C

TOP VIEW

The Intersil HCTS11MS is a Radiation Hardened Triple 3-

Input AND Gate. A high on all inputs forces the output to a

High state.

VCC

The HCTS11MS utilizes advanced CMOS/SOS technology

to achieve high-speed operation. This device is a member of

radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCTS11MS is supplied in a 14 lead Weld Seal Ceramic

ﬂatpack (K sufﬁx) or a Weld Seal Ceramic Dual-In-Line

Package (D sufﬁx).

GND

Truth Table

Functional Diagram

INPUTS

OUTPUTS

NOTE: L = Logic Level Low, H = Logic level High

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 2409.1

7-141

12 3 4 5 6 7

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与HCTS11MS相关器件

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HCTS11MSD	RENESAS	获取价格	HCT SERIES, TRIPLE 3-INPUT AND GATE, CDIP14, WELD SEALED, CERAMIC, DIP-14
HCTS11MSK	RENESAS	获取价格	HCT SERIES, TRIPLE 3-INPUT AND GATE, CDFP14, WELD SEALED, CERAMIC, DFP-14
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HCTS138D	INTERSIL	获取价格	Radiation Hardened Inverting 3-to-8 Line Decoder/Demultiplexer