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HC908LD64AD

更新时间: 2024-09-28 23:54:55
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Addendum to MC68HC908LD64 Technical Data Rev. 2.0

HC908LD64AD 数据手册

 浏览型号HC908LD64AD的Datasheet PDF文件第2页 
Freescale Semiconductor, Inc.  
Order this document  
Semiconductor Products Sector  
Technical Data  
by HC908LD64AD/D  
Rev. 1  
Addendum to  
MC68HC908LD64  
Technical Data  
This addendum provides corrections to:  
MC68HC908LD64 Technical Data  
(Motorola document number MC68HC908LD64/D Rev. 2.0)  
Pa g e 278:  
From:  
Correct WRDY description under 18.7.2 OSD Status Register.  
WRDY — OSD Buffer Write Ready  
This bit is set when the OSD data registers $0062 and $0063, are  
ready to be loaded with new data. The WRDY is cleared after the CPU  
writes to the high byte register, $0063. It becomes set again when the  
OSD circuitry has transferred the content of data registers to the OSD  
RAM. Reset sets this bit.  
1 = OSD data buffers ready for new data  
0 = OSD data buffers busy  
To:  
WRDY — OSD Buffer Write Ready  
This bit is set when the OSD data registers $0062 and $0063, are  
ready to be loaded with new data. The WRDY is cleared after the CPU  
writes to the low byte register, $0062. It becomes set again when the  
OSD circuitry has transferred the content of data registers to the  
display RAM. Reset sets this bit.  
1 = OSD data buffers ready for new data  
0 = OSD data buffers busy  
© Motorola, Inc., 2001  
For More Information On This Product,  
Go to: www.freescale.com  

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