Datasheet > H5TC4G63EFR-PBA

H5TC4G63EFR-PBA

更新时间： 2023-12-06 19:46:30

品牌	Logo	应用领域
海力士 - HYNIX		双倍数据速率
页数	文件大小	规格书
33页	1464K
描述
DDR3

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数据手册

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H5TC4G63EFR-PBA 数据手册

Pin Functional Description

Symbol

Type

Function

Clock: CK and CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of CK.

CK, CK

Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and

device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down

and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any

bank).

CKE, (CKE0),

(CKE1)

Input CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable

during the power on and initialization sequence, they must be maintained during all

operations (including Self-Refresh). CKE must be maintained high throughout read and

write accesses. Input buffers, excluding CK, CK, ODT and CKE, are disabled during power-

down. Input buffers, excluding CKE, are disabled during Self-Refresh.

Chip Select: All commands are masked when CS is registered HIGH.

CS provides for external Rank selection on systems with multiple Ranks.

CS is considered part of the command code.

CS, (CS0),

(CS1), (CS2),

(CS3)

Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the

DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS,

NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x4/x8

configurations. For x16 configuration, ODT is applied to each DQ, DQSU, DQSU, DQSL,

DQSL, DMU, and DML signal. The ODT pin will be ignored if MR1 is programmed to disable

ODT.

ODT, (ODT0),

(ODT1)

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

RAS,

CAS, WE

Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH coincident with that input data during a Write access. DM is sampled

on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by

Mode Register A11 setting in MR1.

DM, (DMU),

(DML)

Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge

BA0 - BA2

A0 - A15

Input command is being applied. Bank address also determines if the mode register or extended

mode register is to be accessed during a MRS cycle.

Address Inputs: Provide the row address for Active commands and the column address for

Read/Write commands to select one location out of the memory array in the respective

bank. (A10/AP and A12/BC have additional functions, see below).

Input

The address inputs also provide the op-code during Mode Register Set commands.

Auto-precharge: A10 is sampled during Read/Write commands to determine whether

Autoprecharge should be performed to the accessed bank after the Read/Write operation.

(HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge

command to determine whether the Precharge applies to one bank (A10 LOW) or all

banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank

addresses.

A10 / AP

A12 / BC

Input

Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst

Input chop (on-the-fly) will be performed.

(HIGH, no burst chop; LOW: burst chopped). See command truth table for details.

Rev. 1.5/ Oct. 2020

1...4 5 678 9 10...33

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与H5TC4G63EFR-PBA相关器件

型号	品牌	获取价格	描述	数据表
H5TC4G63EFR-PBI	HYNIX	获取价格	DDR3
H5TC4G63EFR-RDA	HYNIX	获取价格	DDR3
H5TC4G63EFR-RDI	HYNIX	获取价格	DDR3
H5TC4G63MFR-G7A	HYNIX	获取价格	4Gb DDR3L SDRAM
H5TC4G63MFR-G7C	HYNIX	获取价格	DDR DRAM, 256MX16, 0.3ns, CMOS, PBGA96, HALOGEN FREE AND ROHS COMPLIANT, FBGA-96
H5TC4G63MFR-G7I	HYNIX	获取价格	DDR DRAM, 256MX16, 0.3ns, CMOS, PBGA96, HALOGEN FREE AND ROHS COMPLIANT, FBGA-96
H5TC4G63MFR-H9A	HYNIX	获取价格	4Gb DDR3L SDRAM
H5TC4G63MFR-H9I	HYNIX	获取价格	DDR DRAM, 256MX16, 0.255ns, CMOS, PBGA96, HALOGEN FREE AND ROHS COMPLIANT, FBGA-96
H5TC4G63MFR-PBA	HYNIX	获取价格	4Gb DDR3L SDRAM
H5TC4G83AFR-G7A	HYNIX	获取价格	4Gb DDR3L SDRAM

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