Datasheet > H5ANBG6NAMR-XNC

H5ANBG6NAMR-XNC

更新时间： 2023-12-06 20:08:34

品牌	Logo	应用领域
海力士 - HYNIX		双倍数据速率
页数	文件大小	规格书
43页	1817K
描述
DDR4

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数据手册

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H5ANBG6NAMR-XNC 数据手册

DDR4-2400 Speed Bins and Operations

Speed Bin

DDR4-2400T

17-17-17

CL-nRCD-nRP

Unit

NOTE

Parameter

Symbol

min

max

14.16

(13.75)^5,12

Internal read command to first data

tAA

18.00

Internal read command to first data

with read DBI enabled

tAA_DBI

tRCD

tAA(min) + 3nCK

tAA(max) + 3nCK

14.16

(13.75)^5,12

ACT to internal read or write delay

time

14.16

(13.75)^5,12

PRE command period

tRP

tRAS

tRC

ACT to PRE command period

9 x tREFI

46.16

(45.75)^5,12

ACT to ACT or REF command

period

Normal

CL = 9

Read DBI

CL = 11

(Optional)⁵

1,2,3,4,11

Reserved

CWL = 9

tCK(AVG)

CL = 10

CL = 11

CL = 12

CL = 13

CL = 14

CL = 15

CL = 16

CL = 15

CL = 16

CL = 17

CL = 18

CL = 12

CL = 13

CL = 14

CL = 15

CL = 16

CL = 17

CL = 18

CL = 19

CL = 18

CL = 19

CL = 20

CL = 21

1.5

1.6

ns 1,2,3,4,11

tCK(AVG)

CWL = 9,11

1.25

<1.5

1,2,3,4,8

1,2,3,8

Reserved

CWL =

10,12

1.071

<1.25

1,2,3,4,8

1,2,3,8

CWL =

11,14

0.937

<1.071

1,2,3,4,8

1,2,3,8

1,2,3,4

Reserved

CWL =

12,16

0.833

<0.937

1,2,3

Supported CL Settings

10,11,12,13,14,15,16,17,18

12,13,14,15,16,18,19,20,21

9,10,11,12,14,16

nCK

Supported CL Settings with read DBI

Supported CWL Settings

Rev. 1.0 / Oct.2020

1...34 35 363738 39 40...43

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