Datasheet > GVT71256B36T-6

GVT71256B36T-6

更新时间： 2024-01-20 15:52:26

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
27页	301K
描述
x36 Synchronous SRAM

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中文翻译

获取价格

数据手册

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GVT71256B36T-6 数据手册

CY7C1361A/GVT71256B36

CY7C1363A/GVT71512B18

256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM

and a 2-bit counter for internal burst operation. All synchro-

Features

nous inputs are gated by registers controlled by a positive-

edge-triggered Clock Input (CLK). The synchronous inputs in-

clude all addresses, all data inputs, address-pipelining Chip

• Fast access times: 6.0, 6.5, 7.0, and 8.0 ns

• Fast clock speed: 150, 133, 117, and 100 MHz

• 1 ns set up time and hold time

• Fast OE access times: 3.5 ns and 4.0 ns

• 3.3V –5% and +10% power supply

• 3.3V or 2.5V I/O supply

Enable (CE), depth-expansion Chip Enables (CE and CE ),

Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables

(BWa, BWb, BWc, BWd, and BWE), and Global Write (GW).

However, the CE chip enable input is only available for

TA(GVTI)/A(CY) package version.

• 5V tolerant inputs except I/Os

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data outputs (Q), enabled by

OE, are also asynchronous.

• Clamp diodes to V at all inputs and outputs

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance pin (ADV).

• Multiple chip enables for depth expansion:

three chip enables for TA(GVTI)/A(CY) package version

and two chip enables for B(GVTI)/BG(CY) and

T(GVTI)/AJ(CY) package versions

Address, data inputs, and write controls are registered on-chip

to initiate self-timed WRITE cycle. WRITE cycles can be one

to four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

controls DQa. BWb controls DQb. BWc controls DQc. BWd

controls DQd. BWa, BWb, BWc, and BWd can be active only

with BWE being LOW. GW being LOW causes all bytes to be

written. The x18 version only has 18 data inputs/outputs (DQa

and DQb) along with BWa and BWb (no BWc, BWd, DQc, and

DQd).

• Address pipeline capability

• Address, data and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst se-

quence)

• Automatic power-down for portable applications

• JTAG boundary scan for B and T package version

• Low profile 119-bump, 14-mmx 22-mm PBGA (Ball Grid

Array) and 100-pin TQFP packages

For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-

sions, four pins are used to implement JTAG test capabilities:

Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),

and Test Data-Out (TDO). The JTAG circuitry is used to serially

shift data to and from the device. JTAG inputs use

LVTTL/LVCMOS levels to shift data during this testing mode of

operation. The TA package version does not offer the JTAG

capability.

Functional Description

The Cypress Synchronous Burst SRAM family employs high-

speed, low-power CMOS designs using advanced triple-layer

polysilicon, double-layer metal technology. Each memory cell

consists of four transistors and two high-valued resistors.

The GVT71256B36/CY7C1361A and GVT71512B18/

CY7C1363A SRAMs integrate 262,144x36 and 524,288x18

SRAM cells with advanced synchronous peripheral circuitry

The GVT71256B36 and GVT71512B18 operate from a +3.3V

power supply. All inputs and outputs are LVTTL compatible.

Selection Guide

7C1361A-150

7C1361A-133

7C1363A-133

71256B36-6.5

71512B18-6.5

7C1361A-117

7C1363A-117

71256B36-7

71512B18-7

7C1361A-100

7C1363A-100

71256B36-8

71512B18-8

7C1363A-150

71256B36-6

71512B18-6

Maximum Access Time (ns)

6.0

400

6.5

360

7.0

320

8.0

270

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

May 17, 2000

12 3 4 5 6 7...27

中文翻译

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与GVT71256B36T-6相关器件

型号	品牌	获取价格	描述	数据表
GVT71256B36T-6.5	CYPRESS	获取价格	Standard SRAM, 256KX36, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256B36T-7	ETC	获取价格	x36 Synchronous SRAM
GVT71256B36T-7I	CYPRESS	获取价格	Standard SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10
GVT71256B36T-8	CYPRESS	获取价格	Standard SRAM, 256KX36, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256B36T-8I	CYPRESS	获取价格	Standard SRAM, 256KX36, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256B36TA-6	CYPRESS	获取价格	Cache SRAM, 256KX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256B36TA-6.5	CYPRESS	获取价格	Standard SRAM, 256KX36, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256B36TA-7	CYPRESS	获取价格	Standard SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10
GVT71256B36TA-8	CYPRESS	获取价格	Standard SRAM, 256KX36, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71256B36TA-8I	CYPRESS	获取价格	Standard SRAM, 256KX36, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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