GS88218/36CB-300M
GS88218/36CD-300M
300 MHz
512K x 18, 256K x 36
9Mb SCD/DCD Sync Burst SRAMs
119- and 165-Bump BGA
Military Temp
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
Features
• Military Temperature Range
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
SCD and DCD Pipelined Reads
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip read parity checking; even or odd selectable
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
The GS88218/36C(B/D)-300M is a SCD (Single Cycle
Deselect) and DCD (Dual Cycle Deselect) pipelined
synchronous SRAM. DCD SRAMs pipeline disable commands
to the same degree as read commands. SCD SRAMs pipeline
deselect commands one stage less than read commands. SCD
RAMs begin turning off their outputs immediately after the
deselect command has been captured in the input registers.
DCD RAMs hold the deselect command for one full cycle and
then begin turning off their outputs just after the second rising
edge of clock. The user may configure this SRAM for either
mode of operation using the SCD mode input.
• Automatic power-down for portable applications
• JEDEC-standard 119- and 165-bump BGA packages
Byte Write and Global Write
Functional Description
Applications
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
The GS88218/36C(B/D)-300M is a 9,437,184-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications, ranging
from DSP main store to networking chip set support.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88218/36C(B/D)-300M operates on a 2.5 V or 3.3 V
power supply. All input are 3.3 V and 2.5 V compatible.
Separate output power (V
) pins are used to decouple
DDQ
output noise from the internal circuits and are 3.3 V and 2.5 V
compatible.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Parameter Synopsis
-300M
Unit
tKQ
2.5
3.3
ns
ns
tCycle
Pipeline
3-1-1-1
Curr (x18)
Curr (x32/x36)
280
315
mA
mA
tKQ
5.0
5.0
ns
ns
tCycle
Flow Through
2-1-1-1
Curr (x18)
Curr (x32/x36)
220
245
mA
mA
Rev: 1.00 1/2011
1/34
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
5秒后页面跳转
NTC热敏电阻与PTC热敏电阻的应用原理及应用范围
GTO与普通晶闸管相比为什么可以自关断？为什么普通晶闸管不能呢？从GTO原理、应用范围带你了解原因及推荐型号
LF353数据手册解读：特性、应用、封装、引脚说明、电气参数及替换型号推荐
A4950资料手册解读：特性、应用、封装、引脚功能、电气参数及代换型号
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
