GS8662D20/38CGD-633/550/500
Separate I/O SigmaQuad II+ B4 SRAM Truth Table
Previous
Operation
Current
Operation
A
R
W
D
D
D
D
Q
Q
Q
Q
K
(tn)
K
(tn)
K
(tn)
K
K
(tn)
K
K
(tn+1½
K
K
(tn+2½
K
(tn+2½)
K
K
(tn+3½
K
(tn+4)
(tn-1
)
(tn+1
)
)
(tn+2
)
)
(tn+3
)
)
Deselect
Write
X
X
X
V
V
V
V
1
1
X
1
0
X
0
1
X
1
0
X
0
X
Deselect
Deselect
Deselect
Write
X
D2
X
X
D3
X
—
—
—
—
—
D3
—
D3
—
Hi-Z
Hi-Z
Q2
Hi-Z
Hi-Z
Q3
—
—
—
—
Read
—
—
—
Deselect
Deselect
Read
D0
X
D1
X
D2
—
Hi-Z
Q0
Hi-Z
Q1
—
—
Read
Q2
—
Q3
—
Write
D0
D2
D1
D3
D2
—
Q2
Q3
Write
Read
Q0
Q1
Q2
Q3
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Users should not clock in metastable addresses.
Rev: 1.01 9/2019
7/26
© 2019, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.