Datasheet > 存储 > SRAM> GS841E18AT-133I

GS841E18AT-133I

更新时间： 2024-09-24 04:02:03

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
21页	602K
描述
256K x 18 Sync Cache Tag

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技术参数
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GS841E18AT-133I 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.87
最长访问时间：	11 ns	其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
内存密度：	4718592 bit	内存集成电路类型：	CACHE TAG SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	100
字数：	262144 words	字数代码：	256000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	256KX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm

GS841E18AT-133I 数据手册

GS841E18AT/B-180/166/150/130/100

180 MHz–100 MHz

TQFP, BGA

Commercial Temp

Industrial Temp

256K x 18 Sync

Cache Tag

3.3 V V

3.3 V and 2.5 V I/O

Output registers and the Match output register are provided and

controlled by the FT mode pin (Pin 14). Through use of the FT mode

pin, I/O registers can be programmed to perform pipeline or flow

through operation. Flow Through mode reduces latency.

Features

• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O

supply

• Dual Cycle Deselect (DCD)

• Intergrated data comparator for Tag RAM application

• FT mode pin for flow through or pipeline operation

Byte write operation is performed by using Byte Write Enable (BWE)

input combined with two individual byte write signals BW1-2. In

addition, Global Write (GW) is available for writing all bytes at one

time.

• LBO pin for Linear or Interleave (Pentium and X86) Burst

mode

• Synchronous address, data I/O, and control inputs

• Synchronous Data Enable (DE)

Compare cycles begin as a read cycle with output disabled so that

compare data can be loaded into the data input register. The

comparator compares the read data with the registered input data and a

match signal is generated. The match output can be either in Pipeline

or Flow Through modes controlled by the FT signal.

• Asynchronous Output Enable (OE)

• Asynchronous Match Output Enable (MOE)

• Byte Write (BWE) and Global Write (GW) operation

• Three chip enable signals for easy depth expansion

• Internal self-timed write cycle

Low power (Standby mode) is attained through the assertion of the ZZ

signal, or by stopping the clock (CLK). Memory data is retained

during Standby mode.

• JTAG Test mode conforms to IEEE standard 1149.1

• JEDEC-standard 100-lead TQFP package and 119-BGA

• Pb-Free 100-lead TQFP package available

JTAG boundary scan interface is provided using IEEE standard

1149.1 protocol. Four pins—Test Data In (TDI), Test Data Out

(TDO), Test Clock (TCK) and Test Mode Select (TMS)—are used to

perform JTAG function.

Functional Description

The GS841E18A is a 256K x 18 high performance synchronous DCD

SRAM with integrated Tag RAM comparator. A 2-bit burst counter is

The GS841E18A operates on a 3.3 V power supply and all inputs/

outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate output

(V_DDQ) pins are used to allow both 3.3 V or 2.5 V IO interface.

included to provide burst interface with Pentium^TMand other high

performance CPUs. It is designed to be used as a Cache Tag SRAM,

as well as data SRAM. Addresses, data IOs, match output, chip

enables (CE1, CE2, CE3), address control inputs (ADSP, ADSC,

ADV), and write control inputs (BW1, BW2, BWE, GW, DE) are

synchronous and are controlled by a positive-edge-triggered clock

(CLK).

Dual Cycle Deselect (DCD)

The GS841E18A is a DCD pipelines synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. DCD SRAMs hold the deselect command for one full

cycle and then begin turning off their outputs just after the second

rising edge of the clock.

Output Enable (OE), Match Output Enable, and power down control

(ZZ) are asynchronous. Burst can be initiated with either ADSP or

ADSC inputs. Subsequent burst addresses are generated internally and

are controlled by ADV. The burst sequence is either interleave order

(Pentium^TMor x86) or linear order, and is controlled by LBO.

Parameter Synopsis

–180

-166

-150

-133

-100

cycle

5.5 ns

3.2 ns

6.0 ns

3.5 ns

6.6 ns

3.8 ns

7.5 ns

4.0 ns

10 ns

4.5 ns

Pipeline

3-1-1-1

335 mA 310 mA 275 mA 250 mA 190 mA

Flow

Through

2-1-1-1

8 ns

9.1 ns

8.5 ns

10 ns

11 ns

15 ns

12 ns

15 ns

cycle

210 mA 190 mA 190 mA 140 mA 140 mA

Rev: 1.03 4/2005

1/21

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. * Pentium is a trademark of Intel

12 3 4 5 6 7...21

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与GS841E18AT-133I相关器件

型号	品牌	获取价格	描述	数据表
GS841E18AT-133IT	GSI	获取价格	Cache Tag SRAM, 256KX18, 11ns, CMOS, PQFP100, TQFP-100
GS841E18AT-150	GSI	获取价格	256K x 18 Sync Cache Tag
GS841E18AT-150I	GSI	获取价格	256K x 18 Sync Cache Tag
GS841E18AT-150IT	GSI	获取价格	Cache Tag SRAM, 256KX18, 10ns, CMOS, PQFP100, TQFP-100
GS841E18AT-150T	GSI	获取价格	Cache Tag SRAM, 256KX18, 10ns, CMOS, PQFP100, TQFP-100
GS841E18AT-166	GSI	获取价格	256K x 18 Sync Cache Tag
GS841E18AT-166I	GSI	获取价格	256K x 18 Sync Cache Tag
GS841E18AT-166IT	GSI	获取价格	Cache Tag SRAM, 256KX18, 8.5ns, CMOS, PQFP100, TQFP-100
GS841E18AT-166T	GSI	获取价格	Cache Tag SRAM, 256KX18, 8.5ns, CMOS, PQFP100, TQFP-100
GS841E18AT-180	GSI	获取价格	256K x 18 Sync Cache Tag

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