Datasheet > GS8342T36BD-300I

GS8342T36BD-300I

更新时间： 2023-12-06 20:13:28

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GS8342T36BD-300I 数据手册

GS8342T08/09/18/36BD-400/350/333/300/250

Background

Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.

Therefore, the SigmaDDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are

unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed

Common I/O SRAM data bandwidth in half.

Burst Operations

Read and write operations are "burst" operations. In every case where a read or write command is accepted by the SRAM, it will

respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in

the timing diagrams. This means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often,

if intervening deselect cycles are inserted.

Deselect Cycles

Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to

the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer

and then execute the deselect command, returning the output drivers to high-Z. A high on the LD pin prevents the RAM from

loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer

operations.

SigmaDDR-II B2 SRAM Read Cycles

The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read

command (LD low and R/W high) is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM

produces data out in response to the next rising edge of C (or the next rising edge of K, if C and C are tied high). The second beat

of data is transferred on the next rising edge of C, for a total of two transfers per address load.

SigmaDDR-II B2 SRAM Write Cycles

The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers.

Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command

(LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures

data in on the next rising edge of K, for a total of two transfers per address load.

Rev: 1.02b 8/2017

7/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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