GS8342T08/09/18/36BD-400/350/333/300/250
4M x 9 SigmaDDR-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
NC/SA
(72Mb)
NC/SA
(144Mb)
A
B
CQ
SA
R/W
NC
K
LD
SA
SA
CQ
NC/SA
(288Mb)
NC
NC
NC
SA
K
BW0
SA
SA
NC
NC
DQ4
C
D
E
F
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
NC
NC
NC
NC
NC
V
V
SA
SA
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SS
SS
SS
SS
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DQ5
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQ3
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
DQ6
V
V
V
NC
V
V
V
V
ZQ
REF
DDQ
DDQ
REF
NC
NC
NC
NC
NC
NC
NC
DQ8
SA
NC
DQ2
NC
K
L
V
NC
NC
NC
NC
NC
SA
NC
NC
NC
DQ7
NC
V
V
V
V
V
DQ1
NC
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
NC
SS
SS
SS
SS
NC
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
NC
NC
SA
SA
SA
SA
NC
DQ0
TDI
TCK
C
TMS
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0. SA0 is set to 0 at the beginning
of each access.
2. BW0 controls writes to DQ0:DQ8.
3. A2, A7, and B5 are the expansion addresses.
Rev: 1.02b 8/2017
4/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.