Datasheet > GS8330DW72GC-200

GS8330DW72GC-200

更新时间： 2024-01-16 06:49:20

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
30页	583K
描述
Standard SRAM, 512KX72, 2.25ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209

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GS8330DW72GC-200 技术参数

Preliminary

GS8330DW36/72C-250/200

Double Late Write

Double Late Write means that Data In is required on the third rising edge of clock. Double Late Write is used to implement Pipeline

mode NBT SRAMs.

SigmaRAM Double Late Write with Pipelined Read

Read

Write

Read

Write

Read

Address

ADV

/E₁

Key

Hi-Z

Access

Byte Write Control

The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,

including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle.

Example of x36 Byte Write Truth Table

Function

Read

Write Byte A

Write Byte B

Write Byte C

Write Byte D

Write all Bytes

Write Abort

Rev: 1.00 6/2003

6/30

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

1...3 4 567 8 9...30

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型号	品牌	描述	获取价格	数据表
GS8330DW72GC-200T	GSI	Standard SRAM, 512KX72, 2.25ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209	获取价格
GS8330DW72GC-250IT	GSI	Standard SRAM, 512KX72, 2.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209	获取价格
GS8330DW72GC-250T	GSI	Standard SRAM, 512KX72, 2.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209	获取价格
GS8330LW36C	GSI	36Mb ヒ1x1Lp CMOS I/O Late Write SigmaRAM	获取价格
GS8330LW36C-200	GSI	36Mb ヒ1x1Lp CMOS I/O Late Write SigmaRAM	获取价格
GS8330LW36C-200I	GSI	36Mb ヒ1x1Lp CMOS I/O Late Write SigmaRAM	获取价格