Datasheet > GS82582S36GE-375

GS82582S36GE-375

更新时间： 2023-12-06 20:13:33

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
32页	535K
描述
165 BGA

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数据手册

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GS82582S36GE-375 数据手册

GS82582S18/36GE-400/375/333/300/250

Special Functions

Byte Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a 2-beat data transfer. The x18

version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

Example x18 RAM Write Sequence using Byte Write Enables

Data In Sample Time

BW0

BW1

D0–D8

Data In

D9–D17

Don’t Care

Data In

Beat 1

Beat 2

Don’t Care

Resulting Write Operation

Beat 1

Beat 2

D0–D8

D9–D17

Unchanged

D0–D8

Unchanged

D9–D17

Written

Output Register Control

SigmaSIO DDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the

Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing

of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of

the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs.

Rev: 1.04a 8/2017

6/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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