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GS81302S36GE-200IT PDF预览

GS81302S36GE-200IT

更新时间： 2024-01-07 00:08:05
品牌 Logo 应用领域
GSI 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
38页 526K
描述
DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

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GS81302S36GE-200IT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：17 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.55
最长访问时间：0.45 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：17 mm内存密度：75497472 bit
内存集成电路类型：DDR SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：165字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：2MX36封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.5 mm最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：15 mm

GS81302S36GE-200IT 数据手册

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Preliminary  
GS81302S08/09/18/36E-333/300/250/200/167  
144Mb SigmaSIOTM DDR -II  
Burst of 2 SRAM  
333 MHz–167 MHz  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
1.8 V V  
DD  
1.8 V and 1.5 V I/O  
Features  
• Simultaneous Read and Write SigmaSIO™ Interface  
• JEDEC-standard pinout and package  
• Dual Double Data Rate interface  
• Byte Write controls sampled at data-in time  
• DLL circuitry for wide output data valid window and future  
frequency scaling  
• Burst of 2 Read and Write  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
• Pipelined read operation  
• Fully coherent read and write pipelines  
• ZQ mode pin for programmable output drive strength  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
Bottom View  
165-Bump, 15 mm x 17 mm BGA  
1 mm Bump Pitch, 11 x 15 Bump Array  
JEDEC Std. MO-216, Variation CAB-1  
register clock inputs, C and C. If the C clocks are tied high, the  
K clocks are routed internally to fire the output registers  
instead. Each Burst of 2 SigmaSIO DDR-II SRAM also  
supplies Echo Clock outputs, CQ and CQ, which are  
synchronized with read data output. When used in a source  
synchronous clocking scheme, the Echo Clock outputs can be  
used to fire input registers at the data’s destination.  
SigmaSIO™ Family Overview  
GS81302S08/09/18/36 are built in compliance with the  
SigmaSIO DDR-II SRAM pinout standard for Separate I/O  
synchronous SRAMs. They are 150,994,944-bit (144Mb)  
SRAMs. These are the first in a family of wide, very low  
voltage HSTL I/O SRAMs designed to operate at the speeds  
needed to implement economical high performance  
networking systems.  
Because Separate I/O Burst of 2 RAMs always transfer data in  
two packets, A0 is internally set to 0 for the first read or write  
transfer, and automatically incremented by 1 for the next  
transfer. Because the LSB is tied off internally, the address  
field of a Burst of 2 RAM is always one address pin less than  
the advertised index depth (e.g., the 8M x 18 has a 4M  
addressable index).  
Clocking and Addressing Schemes  
A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous  
device. It employs dual input register clock inputs, K and K.  
The device also allows the user to manipulate the output  
register clock input quasi independently with dual output  
Parameter Synopsis  
-333  
3.0 ns  
0.45 ns  
-300  
3.3 ns  
0.45 ns  
-250  
4.0 ns  
0.45 ns  
-200  
5.0 ns  
0.45 ns  
-167  
tKHKH  
tKHQV  
6.0 ns  
0.5 ns  
Rev: 1.01a 6/2010  
1/38  
© 2007, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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