Datasheet > GM76U256CLLE-12

GM76U256CLLE-12

更新时间： 2024-02-29 09:50:36

品牌	Logo	应用领域
海力士 - HYNIX		静态存储器
页数	文件大小	规格书
11页	175K
描述
x8 SRAM

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数据手册

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GM76U256CLLE-12 数据手册

GM76U256C Series

Notes(WRITE CYCLE):

1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition

among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high

and /WE going high. tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the later of /CS going low to the end of write .

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS,

or /WE going high.

5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state,

input of opposite phase of the output must not be applied because bus contention can occur.

6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high

impedance state.

7. DOUT is the same phase of the latest written data in this write cycle.

8. DOUT is the read data of the new address.

DATA RETENTION CHARACTERISTIC

TA=0°C to 70°C (Normal)

Symbol

VDR

Parameter

Vcc for Data Retention

Test Condition

CS>Vcc-0.2V,

VIN>Vcc-0.2V or VIN<Vss+0.2V

Min

2.0

Typ Max Unit

ICCDR

Data Retention Current

Vcc=3.0V,

0.5

/CS>Vcc - 0.2V,

VIN>Vcc - 0.2V or

VIN< Vss + 0.2V

See Data Retention

LLE

tCDR

Chip Deselect to Data

Retention Time

Operating Recovery Time

Timing Diagram

tRC(2)

Notes

1. Typical values are under the condition of TA = 25°C.

2. tRC is read cycle time.

DATA RETENTION TIMING DIAGRAM

DATA RETENTION MODE

VCC

2.7V

tCDR

2.2V

VDR

CS>VCC-0.2V

VSS

Rev 02 / Apr. 2001

1...5 6 789 10 11

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