Datasheet > GM71C4403CJ-70

GM71C4403CJ-70

更新时间： 2024-02-09 23:32:22

品牌	Logo	应用领域
乐金电子 - LG		内存集成电路光电二极管动态存储器
页数	文件大小	规格书
10页	112K
描述
1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM

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技术参数
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GM71C4403CJ-70 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.74
访问模式：	FAST PAGE WITH EDO	最长访问时间：	70 ns
其他特性：	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-J20	JESD-609代码：	e0
内存密度：	4194304 bit	内存集成电路类型：	EDO DRAM
内存宽度：	4	功能数量：	1
端口数量：	1	端子数量：	20
字数：	1048576 words	字数代码：	1000000
工作模式：	ASYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1MX4
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOJ	封装等效代码：	SOJ20/26,.34
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	刷新周期：	1024
自我刷新：	NO	最大待机电流：	0.001 A
子类别：	DRAMs	最大压摆率：	0.12 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

GM71C4403CJ-70 数据手册

LG Semicon

GM71C4403C

Notes:

AC measurements assume tT = 2ns.

2. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum

recommended value shown in this table, tRAC exceeds the value shown.

Measured with a lode circuit equivalent to 1 TTL loads and 100 pF.

Assumes that tRCD>=tRCD(max) and tRAD<=tRAD(max).

Assumes that tRCD<=tRCD(max) and tRAD>=tRAD(max).

tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the output achieves the

open circuit condition and is not referenced to output voltage levels.

VIH(min) and VIL(max) are reference levels for measuring timing of input signals.Also transition

times are measured between VIH and VIL.

Operation with the tRCD(max) limit insures that tRAC(max) can be met tRCD(max) is specified as a

reference point only: if tRCD is greater than the specified tRCD(max) limit, then access time is

controlled exclusively by tCAC.

Operation with the tRAD(max) limit insures that tRAC(max) can be met tRAD(max) is specified as a

reference point only: if tRAD is greater than the specified tRAD(max) limit, then access time is

controlled exclusively by tAA.

10. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data

sheet as electrical characteristics only if tWCS >=tWCS(min), the cycle is an early write cycle and

the data out pin will remain open circuit (high impedance) throughout the entire cycle if

tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a read-

modify-write and the data output will contain data read from the selected cell if neither of the

above sets of conditions is satisfied, the condition of the data out (at access time) is

indeterminate.

11.

These parameters are referenced to CAS leading edge in early write cycles and to WE leading

edge in delayed write or a read modify write cycle.

12. tRASP defines RAS pulse width in extended data out mode cycles.

Access time is determined by the longest among tAA, tCAC and tACP.

13.

14.

An initial pause of 100us is required after power up followed by a minimum of eight

initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal

refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required.

In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying

data to the device.

15.

16. Test mode operation specified in this data sheet is 2bits test function controlled by control

address bit CA0. This test mode operation can be performed by WE-and-CAS-before-RAS

(WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read

cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the

condition of the output data is low level. In order to end this test mode operation, perform RAS

only refresh cycle or a CAS-before-RAS refresh cycle.

In a test mode read cycle, the value of tRAC, tAA, tCAC, tOAC and tACP is delayed for 2ns to 5ns for

the specified value. These parameters should be specified in test mode cycles by adding the

above value to the specified value in this data sheet.

17.

1...5 6 789 10

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与GM71C4403CJ-70相关器件

型号	品牌	获取价格	描述	数据表
GM71C4403CJ-80	LG	获取价格	1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
GM71C4403CR	LG	获取价格	1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
GM71C4403CR-60	LG	获取价格	1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
GM71C4403CR-70	LG	获取价格	1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
GM71C4403CR-80	LG	获取价格	1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
GM71C4403CT	LG	获取价格	1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
GM71C4403CT-60	LG	获取价格	1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
GM71C4403CT-70	LG	获取价格	1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
GM71C4403CT-80	LG	获取价格	1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
GM71C4403D	LG	获取价格	1,048,576 Words x Bit Organization

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