Datasheet > GM71C18163CL-6

GM71C18163CL-6

更新时间： 2022-11-25 18:42:42

品牌	Logo	应用领域
海力士 - HYNIX		/
页数	文件大小	规格书
11页	114K
描述
1,048,576 WORDS x 16 BIT CMOS DYNAMIC RAM

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数据手册

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GM71C18163CL-6 数据手册

GM71C18163C

GM71CS18163CL

Recommended DC Operating Conditions (TA = 0 ~ +70C)

Symbol

VCC

Parameter

Min

4.5

Typ

Max

5.5

Unit

Supply Voltage

5.0

VIH

Input High Voltage

Input Low Voltage

2.4

6.0

VIL

-1.0

0.8

Note: All voltage referred to Vss.

The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be

on the same level.

Truth Table

Output

Open

Operation

RAS

LCAS UCAS

Notes

1,3

Standby

Valid

Lower byte

1,3

Valid

Read cycle

Upper byte

Valid

Word

Open

Lower byte

Open

Early write cycle

Upper byte

1,2,3

1,3

Open

Word

Undefined

Lower byte

Upper byte

Delayed Write

cycle

Undefined

Valid

Word

Lower byte

H to L L to H

Read-modify

-write cycle

Upper byte

Valid

Open

Word

H to L

CBR Refresh

Self Refresh

(L-series)

Open

Word

1,3

RAS-only

Refresh cycle

Open

Word

1,3

Read cycle

(Output disabled)

Notes: 1. H: High (inactive) L: Low(active) D: H or L

2. tWCS >= 0ns Early write cycle

tWCS <= 0ns Delayed write cycle

3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of

UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However

write OPERATION and output High-Z control are done independently by each UCAS,LCAS.

ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.

Rev 0.1 / Apr’01

1 234 5 6 7...11

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