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GM71C18163CJ-5 PDF预览

GM71C18163CJ-5

更新时间: 2024-01-30 11:01:20
品牌 Logo 应用领域
海力士 - HYNIX 内存集成电路光电二极管动态存储器
页数 文件大小 规格书
11页 114K
描述
x16 EDO Page Mode DRAM

GM71C18163CJ-5 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.75
访问模式:FAST PAGE WITH EDO最长访问时间:50 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHI/O 类型:COMMON
JESD-30 代码:R-PDSO-J42JESD-609代码:e0
内存密度:16777216 bit内存集成电路类型:EDO DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:42
字数:1048576 words字数代码:1000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ42,.44
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified刷新周期:1024
自我刷新:NO最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.19 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

GM71C18163CJ-5 数据手册

 浏览型号GM71C18163CJ-5的Datasheet PDF文件第1页浏览型号GM71C18163CJ-5的Datasheet PDF文件第2页浏览型号GM71C18163CJ-5的Datasheet PDF文件第4页浏览型号GM71C18163CJ-5的Datasheet PDF文件第5页浏览型号GM71C18163CJ-5的Datasheet PDF文件第6页浏览型号GM71C18163CJ-5的Datasheet PDF文件第7页 
GM71C18163C  
GM71CS18163CL  
Recommended DC Operating Conditions (TA = 0 ~ +70C)  
Symbol  
VCC  
Parameter  
Min  
4.5  
Typ  
Max  
5.5  
Unit  
V
Supply Voltage  
5.0  
VIH  
Input High Voltage  
Input Low Voltage  
2.4  
-
-
6.0  
V
VIL  
-1.0  
0.8  
V
Note: All voltage referred to Vss.  
The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be  
on the same level.  
Truth Table  
Output  
Open  
Operation  
RAS  
H
LCAS UCAS  
WE  
D
OE  
D
Notes  
D
L
H
L
L
H
L
D
H
L
L
H
L
L
H
L
L
H
1,3  
Standby  
L
H
L
Valid  
Lower byte  
L
1,3  
L
H
Valid  
Read cycle  
Upper byte  
L
Valid  
H
L
L
L
L
L
L
L
Word  
D
L
Open  
Lower byte  
L
Open  
Early write cycle  
D
D
H
H
H
Upper byte  
1,2,3  
1,2,3  
1,3  
L
Open  
Word  
L
Undefined  
Undefined  
L
Lower byte  
Upper byte  
Delayed Write  
cycle  
H
L
L
L
Undefined  
Valid  
Word  
Lower byte  
L
L
L
H to L L to H  
H to L L to H  
H to L L to H  
Read-modify  
-write cycle  
H
L
L
Upper byte  
Valid  
L
H
L
L
L
Valid  
Open  
Word  
Word  
D
D
D
D
D
D
H to L  
H to L  
H to L  
L
CBR Refresh  
or  
Self Refresh  
(L-series)  
H
Open  
Open  
Word  
Word  
1,3  
L
RAS-only  
Refresh cycle  
Open  
Open  
Word  
H
L
H
D
H
D
H
L
L
1,3  
1,3  
Read cycle  
(Output disabled)  
L
Notes: 1. H: High (inactive) L: Low(active) D: H or L  
2. tWCS >= 0ns Early write cycle  
tWCS <= 0ns Delayed write cycle  
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of  
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However  
write OPERATION and output High-Z control are done independently by each UCAS,LCAS.  
ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.  
Rev 0.1 / Apr’01  

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