Datasheet > GM71C18163C-7

GM71C18163C-7

更新时间： 2022-12-13 07:01:54

品牌	Logo	应用领域
海力士 - HYNIX		/
页数	文件大小	规格书
11页	114K
描述
1,048,576 WORDS x 16 BIT CMOS DYNAMIC RAM

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数据手册

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GM71C18163C-7 数据手册

GM71C18163C

GM71CS18163CL

Capacitance (VCC = 5V+/ - 10%, TA = 25C)

Symbol

CI1

Parameter

Input Capacitance (Address)

Input Capacitance (Clocks)

Output Capacitance (Data-In/Out)

Min

Max

Unit

Note

CI2

1, 2

CI/O

Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. LCAS and UCAS = VIH to disable DOUT

AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ +70C, Note 1, 2, 18, 19, 20)

Test Conditions

Input rise and fall times : 2 ns

Input levels : VIL = 0V, VIH = 3V

Input timing reference levels : 0.8V, 2.4V

Output timing reference levels : 0.8V, 2.0V

Output load : 1TTL gate + CL (100 pF)

(Including scope and jig)

Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)

GM71C(S)18163 GM71C(S)18163 GM71C(S)18163

C/CL-5

C/CL-6

C/CL-7

Unit Note

Symbol

Parameter

Min Max Min Max Min Max

Random Read or Write Cycle Time

RAS Precharge Time

104

124

tRP

CAS Precharge Time

RAS Pulse Width

50 10,000

7 10,000

10,000

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

RSH

CSH

CRP

ODD

DZO

DZC

CAS Pulse Width

10 10,000 13 10,000

Row Address Set up Time

Row Address Hold Time

Column Address Set-up Time

Column Address Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time

RAS Hold Time

11 37

14 45

12 30

14 52

12 35

CAS Hold Time

CAS to RAS Precharge Time

OE to DIN Delay Time

OE Delay Time from DIN

CAS Delay Time from DIN

Transition Time (Rise and Fall)

Rev 0.1 / Apr’01

1 2 3 456 7 8...11

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