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GM1234P PDF预览

GM1234P

更新时间: 2024-09-30 00:04:27
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
90页 2156K
描述
韩国GSSP单片机

GM1234P 数据手册

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GM1234P  
Preliminary_V0.5  
1. KEY FEATURES................................................................................................................................................................... 4  
2. BLOCK DIAGRAM .............................................................................................................................................................. 5  
3. PIN ASSIGNMENTS............................................................................................................................................................. 6  
- 80- PACKAGE...................................................................................................................................................................... 6  
4. PIN DESCRIPTIONS............................................................................................................................................................ 7  
5. ROM OPTION..................................................................................................................................................................... 11  
- ROM OPTION  
(ROM ADRRESS 1FH) ...................................................................................................................... 11  
5. PROGRAM MEMORY ADDRESS SPACE..................................................................................................................... 12  
6. REGISTER FILE ORGANIZATION................................................................................................................................ 13  
- 576 X 8-BITS....................................................................................................................................................................... 13  
7. INTERRUPTS...................................................................................................................................................................... 14  
- INTERRUPT STRUCTURE............................................................................................................................................. 14  
8. SPECIAL FUNCTION REGISTER’S MAP..................................................................................................................... 15  
- BANK 0................................................................................................................................................................................ 15  
- BANK 1................................................................................................................................................................................ 16  
- BANK 2................................................................................................................................................................................ 17  
- BANK 3................................................................................................................................................................................ 18  
9. SYSTEM REGISTERS ....................................................................................................................................................... 19  
- CONFIG REGISTER (CONFIG)  
- DATA MEMORY PAGE SELECTION REGISTER (PGSEL)  
- STATUS REGISTER (STATUS) (03H, 83H, 103H, 183H) ........................................................................ 20  
(00H, 80H, 100H, 180H)....................................................................................... 19  
(05H, 85H, 105H, 185H)........................................ 19  
- CPU CLOCK CONTROL REGISTER (CPUCLK)  
- OSCILLATOR SELCET REGISTER (OSCSEL)  
(01H, 101H)........................................................................... 21  
(81H, 181H)............................................................................ 21  
- SYSTEM CLOCK CIRCUIT DIAGRAM......................................................................................................................... 22  
10. WATCHDOG TIMER ...................................................................................................................................................... 23  
- WATCHDOG TIMER STATUS AND CONTROL REGISTER (WTSCR) (08H, 108H).......................................... 23  
- WATCHDOG TIMER BLOCK DIAGRAM........................................................................................................................ 24  
- NMCLR CIRCUIT DIAGRAM .......................................................................................................................................... 24  
11. I/O PORTS ......................................................................................................................................................................... 25  
- PORT CIRCUIT DIAGRAM.............................................................................................................................................. 25  
- PORT 0 DATA DIRECTION REGISTER HIGH BYTE (DDR0H)  
- PORT 0 DATA DIRECTION REGISTER LOW BYTE (DDR0L)  
(110H)............................................................. 27  
(111H) .............................................................. 28  
- PORT 0 EXTERNAL INTERRUPT REGISTER HIGH BYTE (EINT0H)  
- PORT 0 EXTERNAL INTERRUPT REGISTER LOW BYTE (EINT0L)  
- PORT 0 PULL-UP RESISTOR ENABLE REGISTER (PUR0)  
- PORT 0 EXTERNAL INTERRUPT PWNDING REGISTER (EPND0)  
(112H).......................................... 29  
(113H) ........................................... 30  
(109H) ......................................................... 31  
(114H) ................................................. 32  
- PORT 1 DATA DIRECTION REGISTER HIGH BYTE (DDR1H)  
- PORT 1 DATA DIRECTION REGISTER LOW BYTE (DDR1L)  
- PORT 1 PULL-UP RESISTOR ENABLE REGISTER (PUR1)  
- PORT 2 DATA DIRECTION REGISTER HIGH BYTE (DDR2H)  
- PORT 2 DATA DIRECTION REGISTER LOW BYTE (DDR2L)  
- PORT 3 DATA DIRECTION REGISTER HIGH BYTE (DDR3H)  
- PORT 3 DATA DIRECTION REGISTER LOW BYTE (DDR3L)  
(116H) ............................................................ 33  
(117H)............................................................... 34  
(115H)......................................................... 35  
(106H)........................................................... 36  
(107H)............................................................ 37  
(108H)........................................................... 38  
(109H) ............................................................ 39  
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