FX839P4

更新时间： 2024-01-15 07:02:59

品牌	Logo	应用领域
CMLMICRO		电信集成电路电信电路光电二极管
页数	文件大小	规格书
22页	1141K
描述
Analogue Control Interface

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技术参数
数据手册

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FX839P4 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP,	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.92
Is Samacsys：	N	JESD-30 代码：	R-PDIP-T24
JESD-609代码：	e0	长度：	31.37 mm
功能数量：	1	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	5.59 mm	标称供电电压：	5 V
表面贴装：	NO	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	15.24 mm	Base Number Matches：	1

FX839P4 数据手册

Analogue Control Interface

FX839

1.5

General Description

The device comprises four groups of related functions: variable attenuators, digital to analogue converters, a

multiplexed analogue to digital converter with multiplexer, clock generator and four 8-bit magnitude

comparators with variable reference levels. These functions are all controlled by the 'C-BUS' serial interface

and are described below:

Variable Attenuators

The two variable attenuators have a range of 0 to -12dB and 0 to -6dB respectively and may be controlled

independently.

Digital to Analogue Converters

Three DACs are provided with default resolutions of 8 bits, which are defined at the initial chip reset. In this

mode the 'C-BUS' data is transferred in a single byte. An option is provided to define any one or more of the

DAC resolutions to be 10 bits, then the DAC requires the transfer of two 'C-BUS' data bytes.

The upper and lower DAC reference voltages are defined internally as AV and V respectively. The output

voltage is expressed as:

OUT

= AV x (DATA / 2 ) [Volts]

Where, n is the DAC resolution (8 or 10 bits) and DATA is the decimal value of the input code. For example: n

= 8 and binary code = 11111111 therefore DATA = 255

OUT

= AV x (255 / 256) [Volts]

Any one of the three DAC input latches may be loaded by sending an address/command byte followed by one

or two data bytes to the 'C-BUS' interface. The data is then latched and the static voltage is updated at the

appropriate output.

When a DAC is disabled its output is defined as open-circuit.

Analogue to Digital Converter and ADC Clock Generator

A single successive approximation ADC is provided with four multiplexed inputs. In order to minimise the

sampling time of each input channel, a Sample and Hold circuit has not been included at the input of the ADC.

For the sampling to be accurate the input signal should not change significantly during the conversion time.

Since the typical application is for the monitoring of slowly changing control voltages this should not present

any problems. The maximum signal 'linear rate of change', 'S', can be quantified by the following expression

(for a maximum 1 bit error):

S = AV x f

/ (2 x 1000 x (10 + 2)) [mV/µs]

adc_clk

Where f

is the internal ADC clock frequency.

adc_clk

The programmable clock generator is intended to be flexible, making use of an external system clock signal or

a dedicated crystal. This clock signal is scaled to provide the internal ADC clock frequency (f ). The user

adc_clk

has full control of the frequency scaling factor and this should be chosen such that the input clock frequency, at

the XTAL/CLOCK pin, divided by this factor is no more than 1MHz.

Consumer Microcircuits Limited

1997

D/839/4

1...4 5 678 9 10...22

中文翻译

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