FT28HC256
PIN CONFIGURATION
TSOP
Plastic DIP
CERDIP
Flat Plastic
SOIC
LCC
PLCC
A
A
A
A
A
A
A
I/O
I/O
I/O
NC
V
SS
NC
I/O
I/O
I/O
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
3
4
5
2
1
0
0
1
2
6
A
A
A
A
28
27
26
25
24
23
22
21
20
19
18
17
7
12
14
1
28
27
26
25
24
23
22
V
CC
14
12
4 3
2 1
32 31 30
29
A
2
WE
5
A
8
NC
V
A
A
A
A
A
A
A
6
5
4
3
2
1
0
A
A
A
A
A
A
A
A
3
7
6
5
4
3
2
1
0
A
FT28HC256
13
CC
6
7
28
27
A
9
4
NC
A
8
3
4
5
6
7
A
WE
11
5
A
A
9
A
13
NC
OE
8
9
26
25
6
A
8
FT28HC256
11
A
9
7
(Top View)
OE
A
CE
A
11
FT28HC256
10
11
24
23
10
A
8
21
20
19
18
17
16
15
OE
10
A
10
CE
I/O
9
CE
I/O
12
13
22
21
7
NC
10
11
12
13
14
7
I/O
I/O
0
6
PGA
I/O
I/O
I/O
I/O
I/O
I/O
14 15 16 17 18 19 20
0
1
2
6
5
4
3
I/O
12
I/O
13
I/O
I/O
17
I/O
18
1
2
3
5
6
7
15
I/O
V
I/O
A
10
V
I/O
I/O
19
0
0
2
SS
4
SS
11
14
16
A
A
CE
20
A
10
21
1
9
7
5
8
FT28HC256
A
A
OE
22
A
23
3
4
11
8
6
A
A
2
V
A
9
24
A
25
5
12
7
CC
28
A
A
WE
27
A
13
26
A
6
14
4
3
1
(Bottom View)
PIN DESCRIPTIONS
Addresses (A –A )
Write Enable (WE)
The Write Enable input controls the writing of data to
the FT28HC256.
0
14
The Address inputs select an 8-bit memory location
during a read or write operation.
PIN NAMES
Symbol
A –A
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Chip Enable (CE)
0
14
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consump-
tion is reduced.
I/O –I/O
0
7
WE
CE
OE
Output Enable (OE)
The Output Enable input controls the data output b uff-
ers, and is used to initiate read operations.
V
CC
V
Ground
SS
Data In/Data Out (I/O –I/O )
0
7
NC
No Connect
Data is written to or read from the FT28HC256 through
the I/O pins.
Characteristics subject to change without notice. 2 of 23
REV 1.0