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FPD87346VS/NOPB

更新时间： 2024-01-06 23:44:02

品牌	Logo	应用领域
美国国家半导体 - NSC		控制器
页数	文件大小	规格书
3页	106K
描述
FPD87346VS/NOPB

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技术参数
数据手册

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FPD87346VS/NOPB 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.84	JESD-609代码：	e3
湿度敏感等级：	3	端子面层：	Matte Tin (Sn)
Base Number Matches：	1

FPD87346VS/NOPB 数据手册

PRELIMINARY

October 2003

FPD87346

Low EMI, Low Dynamic Power (SVGA) XGA/WXGA

TFT-LCD Timing Controller with Reduced Swing

™

Differential Signaling (RSDS ) Outputs

General Description

Features

™

n Reduced Swing Differential Signalling (RSDS ) digital

bus reduces dynamic power, EMI and bus width from

the timing controller

The FPD87346 is a timing controller that combines an LVDS

single pixel input interface with National’s Reduced Swing

™

Differential Signaling (RSDS ) output driver interface for

(SVGA) XGA and Wide XGA resolutions. It resides on the

TFT-LCD panel and provides the data buffering and control

signal generation for (SVGA) XGA, and Wide XGA graphic

n LVDS single pixel input interface system

n Input clock range from 40 MHz to 85 MHz

™

n Drives RSDS Column Drivers at 170 Mb/s with an

™

modes. The RSDS path to the column driver contributes

85 MHz clock (Max.)

toward lowering radiated EMI and reducing system dynamic

power consumption.

n Virtual 8 bit color depth in FRC/Dithering mode

n Single narrow 9-bit differential Source Driver bus

minimizes width of Source PCB

n Ability to drive (SVGA) XGA and Wide XGA TFT-LCD

Systems

™

This single RSDS bus conveys the 8-bit color data for

(SVGA) XGA, and Wide XGA panels at 170 Mb/s when using

VESA 60 Hz standard timing.

n Failure detect function in DE mode

n CMOS circuitry operates from a 3.0V–3.6V supply

System Diagram

20061501

FIGURE 1. Block Diagram of the LCD Module

™

RSDS is a trademark of National Semiconductor Corporation

DS200615

www.national.com

12 3

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