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FMS6243MTC14X PDF预览

FMS6243MTC14X

更新时间： 2024-01-16 18:41:21
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
10页 467K
描述
Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control

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FMS6243MTC14X 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP14,.25
针数：14Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.64
商用集成电路类型：CONSUMER CIRCUITJESD-30 代码：R-PDSO-G14
长度：5 mm功能数量：1
端子数量：14最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Other Consumer ICs最大压摆率：34 mA
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
表面贴装：YES温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

FMS6243MTC14X 数据手册

 浏览型号FMS6243MTC14X的Datasheet PDF文件第3页浏览型号FMS6243MTC14X的Datasheet PDF文件第4页浏览型号FMS6243MTC14X的Datasheet PDF文件第5页浏览型号FMS6243MTC14X的Datasheet PDF文件第7页浏览型号FMS6243MTC14X的Datasheet PDF文件第8页浏览型号FMS6243MTC14X的Datasheet PDF文件第9页 
The same circuits can be used with AC-coupled outputs  
if desired. Here is the DC-coupled input with an AC-cou-  
pled output.  
where:  
VO = 2Vin + 0.280V  
I
CH = (ICC / 3) + (VO/RL)  
VIN = RMS value of input signal  
ICC = 24mA  
Vs = 5V  
0V - 1.4V  
DVD or  
STB  
LCVF  
Clamp  
Inactive  
75Ω  
RL = channel load resistance  
SoC  
Board layout can also affect thermal characteristics.  
Refer to the Layout Considerations section for more  
information.  
DAC  
Output  
The FMS6243 is specified to operate with output cur-  
rents typically less than 50mA, more than sufficient for a  
dual (75Ω) video load. Internal amplifiers are current lim-  
ited to a maximum of 100mA and should withstand brief-  
duration, short-circuit conditions; however, this capability  
is not guaranteed.  
Figure 9. DC-Coupled Inputs, AC-Coupled Outputs  
External video  
0V - 1.4V  
source must  
be AC coupled  
0.1μ  
220μ  
LCVF  
Clamp  
Active  
75Ω  
Group Delay Adjustment  
75Ω  
The FMS6243 has the ability to independently adjust  
each channel for Sin X/X group delay and Chroma/Luma  
delay. This is accomplished by placing a capacitor from  
the device delay adjust pin to ground. The group delay  
can be adjusted from the nominal of +10ns to -80ns. This  
means that, under a nominal situation, a video system  
may have an overall group delay measurement of  
+50ns. If the system specification is +40ns, the  
FMS6243 could be used to decrease this group delay to  
fall well within specification with a guard band to allow for  
system variation.  
Figure 10. AC-coupled Inputs and Outputs  
External video  
source must  
7.5MΩ  
0.1μ  
be AC coupled  
LCVF  
Bias  
Input  
75Ω  
Adding a 50pF capacitor to the desired channel DCap  
pin (see Figure 15) generates a -20ns delay through the  
FMS6243, which, when summed with the +50ns of the  
system, gives a new system overall group delay of  
+30ns. It now meets the system specification with a  
+10ns guard band for system group delay variation.  
75Ω  
500mV +/-350mV  
Figure 11. Biased AC-Coupled Inputs with  
AC-Coupled Outputs  
Figure 12 shows the effect on group delay by adding  
capacitance to the FMS6243 DCap pins. The correct  
capacitor can be chosen by determining the format of the  
video system (NTSC 3.58 or PAL 4.43), then choosing  
the desired group delay to sum with overall system  
delay. The desired delay and format line intersection is  
the delay capacitor needed for the DCap pins.  
NOTE: The video tilt or line time distortion is dominated  
by the AC-coupling capacitor. The value may need to be  
increased beyond 220µF to obtain satisfactory operation  
in some applications.  
Power Dissipation  
40  
400kHz Ref  
4.43MHz  
3.58MHz  
The output drive configuration must be considered when  
calculating overall power dissipation. Care must be taken  
not to exceed the maximum die junction temperature.  
The following example can be used to calculate power  
dissipation and internal temperature rise:  
20  
0
10pF  
20pF  
30pF  
40pF  
50pF  
60pF  
70pF  
80pF  
-20  
-40  
-60  
-80  
-100  
Tj = TA + Pd • ΘJA  
where:  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
Frequency (MHz)  
Pd = PCH1 + PCH2 + PCH3  
and PCHx = Vs • ICH - (VO2/RL)  
Figure 12. Group Delay vs. Delay Cap. Value  
© 2007 Fairchild Semiconductor Corporation  
FMS6243 Rev. 1.0.0  
www.fairchildsemi.com  
6
1...345678910

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