Datasheet > FMS6243MTC14X

FMS6243MTC14X

更新时间： 2024-02-12 15:45:51

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		驱动器
页数	文件大小	规格书
10页	467K
描述
Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control

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FMS6243MTC14X 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	TSSOP, TSSOP14,.25
针数：	14	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.64
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	R-PDSO-G14
长度：	5 mm	功能数量：	1
端子数量：	14	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP14,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	Other Consumer ICs	最大压摆率：	34 mA
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm	Base Number Matches：	1

FMS6243MTC14X 数据手册

Application Information

The FMS6243 Low-Cost Video Filter (LCVF) provides

6dB gain from input to output. In addition, the input is

slightly offset to optimize the output driver performance.

The offset is held to the minimum required value to

decrease the standing DC current into the load. Typical

voltage levels are shown in the diagram below:

I/O Configurations

For DC-coupled DAC drive with DC-coupled outputs, use

this configuration:

Figure 5. DC-Coupled Inputs and Outputs

Alternatively, if the DAC’s average DC output level

causes the signal to exceed the range of 0V to 1.4V, it

can be AC-coupled as follows:

Figure 6. AC-Coupled Inputs, DC-Coupled Outputs

When driven by an unknown external source or a

SCART switch with its own clamping circuitry, the inputs

should be AC-coupled like this:

Figure 3. Typical Voltage Levels

The FMS6243 provides an internal diode clamp to sup-

port AC-coupled input signals. If the input signal does not

go below ground, the input clamp does not operate. This

allows DAC outputs to directly drive the FMS6243 without

an AC coupling capacitor. When the input is AC-coupled,

the diode clamp sets the sync tip (or lowest voltage) just

below ground. The worst-case sync tip compression due

to the clamp can not exceed 7mV. The input level set by

the clamp combined with the internal DC offset keeps the

output within its acceptable range.

For symmetric signals like Chroma, U, V, Pb, and Pr, the

average DC bias is fairly constant and the inputs can be

AC-coupled with the addition of a pull-up resistor to set

the DC input voltage. DAC outputs can also drive these

signals without the AC-coupling capacitor. A conceptual

illustration of the input clamp circuit is shown below:

Figure 7. SCART with DC-Coupled Outputs

The same method can be used for biased signals with

the addition of a pull-up resistor to make sure the clamp

never operates. The internal pull-down resistance is

800kΩ ±20% so the external resistance should be

7.5MΩ to set the DC level to 500mV.

Figure 4. Input Clamp Circuit

Figure 8. Biased SCART with DC-Coupled Outputs

FMS6243 Rev. 1.0.0

www.fairchildsemi.com

1 2 3 456 7 8...10

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